CPU And DSP(高泽华).ppt

? Eight low bank address registers (R0–R7) ? Eight high bank address registers (R8–R15), or alternatively, eight base address registers (B0–B7) ? Two stack pointers (NSP, ESP), only one of which is active at a time (SP) ? Four offset registers (N0–N3) ? Four modifier registers (M0–M3) ? A modifier control register (MCTL) ? Two address arithmetic units (AAU) ? One bit mask unit (BMU) 330HiFi： 32 registers，3 MUL/MAC，SIMD，VLIW，Advanced Instructions, 32 bus cache ZSP500 16+8+ registers，2MUL/MAC, SIMD, SuperScalar, 4 instructions group ,128-bit address bus,64x2 data bus TCM TeakliteIII 8+8+ registers, 2MUL/MAC, SIMD, SuperScalar, 2~3 instructions group, 32x2 address bus,32x2 data bus TCM Sc140e 16+8+4+4 registers, 4MUL/MAC, SIMD, SuperScalar, MIPS24K RISC 24x24 or 16x16 single MUL/MAC 24x24 dual MUL/MAC 32x16 single or dual MUL/MAC Add, subtract, advanced compare (all are scalar, more are 24-bit, some can have Q) 32-bit Variable-Length Decode Table Entry 16-bit Variable-Length Decode Table Entry Normalize Shift Amount Operations Truncate, Round, Saturate, Convert, and Move Operations Selection and Permutation Operations Bitwise Logical Operations Zero Operations 5-stage pipeline with 64/24/16-bit ISA 2-issue VLIW Base ALU, barrel shifter 32x32 integer single-cycle multiplier 32-bit integer divider Miscellaneous (NSA, MIN/MAX, SignExtend) instructions 32 entry AR register file Integrated interrupt controller with 22 interrupts with 6 priority levels Integrated timer with 3 timers 4K, 2-way associative instruction cache 8K, 2-way associative write-back data cache Single local, tightly-coupled instruction RAM (can be populated from 0 to 128KB) Dual local, tightly-coupled instruction RAM (can be populated from 0 to 128KB) ？？64bit load The ZSP500 core is a four-way superscalar, dual MAC digital signal processor RISC-based superscalar architecture The ZSP500 architecture can prefetch eight instruction words each clock cycle. Running at 250 MHz, a ZSP500-based