hazards(结构冒险大多发生在).pptVIP

MAINAK CS422 MAINAK CS698K More Pipeline Basic RISC Pipelining Basic idea: Each instruction spends 1 clock cycle in each of the 5 execution stages. During 1 clock cycle, the pipeline can process (in different stages) 5 different instructions. Simple RISC Datapath Description of Pipe Stages Hazards The hazards of pipelining Pipeline hazards prevent next instruction from executing during designated clock cycle There are 3 classes of hazards: Structural Hazards: Arise from resource conflicts HW cannot support all possible combinations of instructions Data Hazards: Occur when given instruction depends on data from an instruction ahead of it in pipeline Control Hazards: Result from branch, other instructions that change flow of program (i.e. change PC) How do we deal with hazards? Often, pipeline must be stalled Stalling pipeline usually lets some instruction(s) in pipeline proceed, another/others wait for data, resource, etc. Stalls and performance Stalls impede(阻止) progress of a pipeline and result in deviation from 1 instruction executing/clock cycle Pipelining can be viewed to: Decrease CPI or clock cycle time for instruction Let’s see what affect stalls have on CPI… CPI pipelined = Ideal CPI + Pipeline stall cycles per instruction 1 + Pipeline stall cycles per instruction Ignoring overhead and assuming stages are balanced: Even more pipeline performance issues! This results in: Which leads to: If no stalls in ideal case speedup = = number of pipeline stages 1. Structural hazards Most common instances of structural hazards(结构冒险大多发生在): When a functional unit not fully pipelined(完全流水) When some resource not duplicated enough One way to avoid structural hazards is to duplicate resources Pipelines stall result of hazards, CPI increased from the usual “1” An example of a structural hazard How is it resolved? Or alternatively… Remember the common case! But, in some cases it may be better to allow them than to eliminate them. These are situations a computer