基于电流测试的cmos sram测试方法研究-research on cmos sram test method based on current test.docx

基于电流测试的 CMOS SRAM 测试方法研究摘 要CMOS SRAM 作为 IC 领域中一个极为重要的部分，其测试研究工作对于保证集成 电路产品的质量具有重要的实际应用价值。传统的基于电压测试的测试方法已得到了 广泛的应用，但这种方法仍然无法有效地检测某些故障。作为电压测试方法的补充， 电流测试方法能够提高故障覆盖率和产品的可靠性。动态电流提供了一个观测电路内 部开关性能的新窗口，动态电流测试方法为进一步提高故障覆盖率提供了可能。本文在深入研究 SRAM 结构原理、工作原理的基础上，设计了 4-bit X 4-bit CMOS SRAM，作为对 SRAM 进行动态电流测试研究的基础电路。在深刻理解 SRAM 故障模型基 础上，通过故障注入和转换写操作或者读操作，完成了对 SRAM 开路故障、短路故障、 图形敏感故障的故障模拟。通过 HSPICE 软件观测了故障单元与无故障单元的动态电 源电流波形。通过比较二者的动态电源电流波形图说明了用动态电流检测 CMOS SRAM 故障是可行的。在此基础上设计了 SRAM 电流可测试性结构，以有效地检测 CMOS SRAM 这些故障。仿真结果证明：本文所提出的电流测试方法作为传统电压测试方法的补充，可以 有效地检测 CMOS SRAM 开路故障和短路故障，而不需要额外的测试序列。关键词：CMOS SRAM动态电流测试故障模型故障模拟Study on the Testing Method of CMOS SRAM based on Current TestingAbstractAs an extremely important part of IC area, the research on the testing of CMOS SRAM is of great practical value to the quality of IC product .The traditional testing method based on voltage has been widely used in practice. But there are still some defects in circuit that can not be detected by traditional testing method. As a supplement to this method, current testing method can increase the fault coverage and make the higher reliability of product. The dynamic current has offered a new window of observing switch performance of circuit. Dynamic current testing ( IDDT ) method makes possible furtherincreasing the fault coverage.A 4-bit X 4-bit CMOS SRAM is designed as the base circuit of dynamic current testing study on CMOS SRAM on the basis of the comprehension of SRAM structure and operational principle in this paper. Fault simulation of open faults, short faults and pattern sensitive faults is accomplished by injecting faults and transition write operation and read operation on the basis of the fault models of SRAM. The dynamic power supply current wave of fault cell and fault-free cell can be observed by HSPICE software. It is shown that detecting CMOS SRAM fault using dynamic current is feasible by comparing the difference of their dynamic power supply current waveform. And then the SRAM current testable