Digital Logical Circuit（俞鹤伟）chapter5-a.pptVIP

* Digital Logic Chapter5 – Hardware Description Languages * Introduction Hardware description language (HDL): allows designer to specify logic function only. Then a computer-aided design (CAD) tool produces the optimized gates. Most commercial designs is built using HDLs Three leading HDLs: ABEL (Advanced Boolean Equation Language) Started as a synthesizable design language Specifically targeted to PAL devices VHDL Verilog Started out as simulation languages Allowing a digital system’s hardware to be described and its operations to be simulated on a computer * 5.1.2 HDL Tool Suites Text editor Compiler Synthesizer Simulator Transforms HDL code into a netlist describing the hardware (i.e., a list of gates and the wires connecting them) -Input values are applied to the circuit -Outputs checked for correctness -Millions of dollars saved by debugging in simulation instead of hardware 5.1 HDL-Based Digital Design Parsing the HDL program, finding syntax errors * hierarchy/ block diagram coding compilation simulation/ verification synthesis fitting/ place+route timing verification 5.1.3 HDL-Based Design Flow Design flow—steps in an HDL-based design process 5.3 The VHDL Hardware Description Language VHSIC Hardware Description Language Very High Speed Integrated Circuit Development sponsored by the IEEE and the US DoD in mid-1980s Based on ADA (somehow similar to Pascal) A simple example : The Full Adder Full Adder Cin Cout S B A library IEEE; use IEEE.std_logic_1164.all; entity full_adder is -- a one-bit full adder port ( A, B, Cin: in BIT; -- Three binary inputs S, Cout: out BIT); -- Two binary outputs end full_adder; entity declaration Example: The Full Adder architecture full_adder_arch of full_adder is begin S = A xor B xor Cin; Cout = (B and Cin) or (A and Cin) or (A and B); end full_adder_arch; Cout = BCin + ACin + AB S = A’BCin’ + A’B’Cin + AB’Cin’ + ABCin = A’(BCin’ + B