Digital Logical Circuit（俞鹤伟）chapter5-b.pptVIP

architecture full_adder_arch of full_adder is signal X_xor_Y, X_CIN, Y_CIN,X_Y: STD_LOGIC; component XOR2 port (I0,I1: in STD_LOGIC; O: out STD_LOGIC); end component; component AND2 port (I0,I1: in STD_LOGIC; O: out STD_LOGIC); end component; component OR3 port (I0,I1,I2: in STD_LOGIC; O: out STD_LOGIC); end component; begin U1: XOR2 port map (X,Y,X_xor_Y); U2: AND2 port map (X,CIN,X_CIN); U3: AND2 port map (Y,CIN,Y_CIN); U4: AND2 port map (X,Y,X_Y); U5: XOR2 port map (X_xor_Y,CIN,S); U6: OR3 port map (X_CIN,Y_CIN,X_Y,COUT); end full_adder_arch; Second part: Solution of the practice Generate Statement The generate statement creates multiple copies of a particular structure using a kind of “for loop,” without having to write all of the component instantiations individually. label: for identifier in range generate concurrent-statement end generate; Syntax of a for-generate loop: Generate Statement Example: 8-bit Inverter library IEEE; use IEEE.std_logic_1164.all; entity inv8 is port ( X: in STD_LOGIC_VECTOR (1 to 8); Y: out STD_LOGIC_VECTOR (1 to 8) ); end inv8; architecture inv8_arch of inv8 is component INV port (I: in STD_LOGIC; O: out STD_LOGIC); end component; begin g1: for b in 1 to 8 generate U1: INV port map (X(b), Y(b)); end generate; end inv8_arch; X(1) X(3) X(4) X(5) X(6) X(7) X(8) X(2) Y(1) Y(3) Y(4) Y(5) Y(6) Y(7) Y(8) Y(2) inv8 Generic Constants A generic constant is defined with a generic declaration. The value of the constant is deferred until the entity is instantiated. In an instantiation of an entity, values are assigned to the generic constants using a generic map clause (similar to a port map). entity entity-name is generic (constant-names : constant-type; constant-names : constant-type; … constant-names : constant-type); port (signal-names : mode signal-type; signal-names : mode signal-type;