Digital Logical Circuit（俞鹤伟）chapter8.pptVIP

* * * * * * * * * * * * * * * * A module-11 counter (using LD_L) LD_L Make a module-x counter using LD_L 5: 0101 General cascading connections for 74x163-based counters CLK CLR LD ENP ENT A B C D QA QB QC QD RCO 74X163 CLK CLR LD ENP ENT A B C D QA QB QC QD RCO 74X163 Q0 Q1 Q2 Q3 D4 D5 D6 D7 RCO4 Q4 Q5 Q6 Q7 RCO8 D0 D1 D2 D3 CLOCK RESET_L LOAD_L CNTEN A shift register is an n-bit register with a provision for shifting its stored data by one position at each tick of the clock. 8.5 Shift register 8.5.1 Shift register structure CK Q D CLOCK CK Q D CK Q D . . . SERIN SEROUT CK Q D CLOCK CK Q D CK Q D . . . SERIN NQ 2Q 1Q Serial-in serial-out Serial-in parallel-out Right Shift Register Shift register Left Shift Register Shift register 8.5.2 MSI Shift Register CLK CLR S1 S0 D C B A QD QC QB QA 74X194 LIN RIN INPUT NEXT STATE FUNCTION S1 S0 QA* QB* QC* QD* Hold 0 0 QA QB QC QD Shift right 0 1 RIN QA QB QC Shift left 1 0 QB QC QD LIN Load 1 1 A B C D 4-bit bidirectional, parallel-in, parallel-out shift register 8.5.3 Shift Register Counter A shift register can be combined with combinational logic to form a state machine whose state diagram is cyclic. Unlike a binary counter, a shift-register counter does not count in an ascending or descending binary sequence, but it is useful in many “control” applications . 8.5.4 Ring Counter Ring Counter: using an n-bit shift register to obtain a counter with n states. Ring Counter Major problem: not robust Shift Register Counter Self-correcting counter: all abnormal states have transitions leading to normal states. Shift Register Counter Using an n-1-input NOR gate, an n-bit self-correcting ring counter can correct an abnormal state within n - 1 clock ticks State diagram for a self-correcting ring counter Supplementary Content Examples of sequential logic application