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EDA 实验VHDL 程序
(1)1011状态机
library ieee;
use ieee.std_logic_1164.all;
entity asdf is
port(xi,rst,clk:bit;
zo:out bit);
end asdf;
architecture asdf of asdf is
type state is (zero,one, two,three,four);
signal pre_state,nx_state:state;
begin
process(rst,clk)
begin
if(rst=1)then
pre_state=zero;
elsif (clkevent and clk=1)then
pre_state=nx_state;
end if;
end process;
process(pre_state)
begin
case pre_state is
when zero=zo=0;
if(xi=1) then nx_state=one;
else nx_state=zero;
end if;
when one=zo=0;
if(xi=0) then nx_state=two;
else nx_state=one;
end if;
when two=zo=0;
if(xi=1) then nx_state=three;
else nx_state=zero;
end if;
when three=zo=0;
if(xi=1) then nx_state=four;
else nx_state=two;
end if;
when four=zo=1;
if(xi=1) then nx_state=one;
else nx_state=two;
end if;
end case;
end process;
end asdf;
2模24计数器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity couter2 is
port(rst,clk: in std_logic;
Q: out std_logic_vector(0 to 4));
end couter2;
architecture couter2 of couter2 is
begin
process(rst,clk)
variable d1:integer range 0 to 23;
begin
if(rst=0)then
d1:=0;
elsif(clkevent and clk=1) then
d1:=d1+1;
if(d123)then
d1:=0;
end if;
end if;
Q=conv_std_logic_vector(d1,5);
end process;
end couter2;
3百进制数码管显示
library ieee;
use ieee.std_logic_1164.all;
entity counter1 is
port(clk,rst:in std_logic;
output1,output2:out std_logic_vector(0 to 6));
end counter1;
architecture bhv of counter1 is
begin
process(rst,clk)
variable t1,t2:integer range 0 to 10;
begin
if(rst=1)then
t1:=0; t2:=0;
elsif(clkevent and clk=1)then
t1:=t1+1;
if(t19)then t1:=0; t2:=t2+1;
if(t29) then t2:=0;
end if;
end if;
end if;
case t1 is
when 0=output1=1111110;
when 1=output1=0110000;
when 2=output1=1101101;
when 3=output1=1111001;
when
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