EDA(中国地质大学 )课堂作业.doc

1题：4选1生成8个 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity ff is port(ain:in std_logic_vector(3 downto 0); sel:in std_logic_vector(1 downto 0); y:out std_logic ); end ; architecture bhv of ff is begin y=ain(conv_integer(sel)); end bhv; library ieee; use ieee.std_logic_1164.all; package newtype is type ary84 is array (7 downto 0,3 downto 0) of std_logic; type ary82 is array (7 downto 0,1 downto 0) of std_logic; End package; library ieee; use ieee.std_logic_1164.all; use work.newtype.all; entity f is port(ain84:in ary84; sel84:in ary82; y84:out std_logic_vector(7 downto 0); count:out std_logic); end ; architecture t of f is component ff is port(ain:in std_logic_vector(3 downto 0); sel:in std_logic_vector(1 downto 0); y:out std_logic ); end component; signal y841: std_logic_vector(7 downto 0); begin gen1:for n in 0 to 7 generate ux: ff port map(ain84(n,3)ain84(n,2)ain84(n,1)ain84(n,0), sel84(n,1)sel84(n,0),y841(n)); end generate; y84=y841; process(y841) variable tmp:std_logic; begin tmp:=1; for i in 0 to 7 loop tmp:=tmp and y841(i); end loop; count=tmp; end process; end architecture; 2题：5-4状态机 library ieee; use ieee.std_logic_1164.all; entity ff is port(clk,res:in std_logic; ina:in std_logic_vector(0 to 2); outa:out std_logic_vector(3 downto 0)); end ff; architecture f1 of ff is type sta is(s0,s1,s2,s3); signal cs,ns:sta; begin reg:process(clk,res) begin if res=1 then cs=s0; elsif clkevent and clk=1 then cs=ns;end if; end process; com:process(cs,ina) begin case cs is when s0= ns=s1; if ina=101 then outa=0010; elsif ina=111 then outa=1100; end if; when s1= outa=1001; if ina=000 then ns=s1; elsif ina=110 then ns=s2;else ns=s2; end if; when s2= outa=1111; if ina=011 then ns=s1; elsif ina=100 then ns=s2; else ns=s3; end if; when s3= ns=s0; if ina=101 then outa=1101; els