原创毕业论文时分制指令响应式传输数据帧的设计与实现.doc

时分制指令-响应式传输数据帧的设计与实现 摘要 近年来随着现代计算机技术和微电子技术的进一步结合和发展，使得集成电路的设计出现了两个分支。一个是传统的更高集成度的集成电路的进一步研究；另一个是利用高层次VHDL等硬件描述语言对可编程逻辑器件（FPGA/CPLD）进行专门设计，使之成为专用集成电路（ASIC），这不仅大大节省了设计和制造时间，而且对设计者，不必考虑集成电路制造工艺，目前已成为电子系统设计的一项主流技术，也即是电子设计自动化（EDA）技术。如今，FPGA器件广泛用于通信、自动控制，信息处理等诸多领域。 本文所涉及是军用飞机中数据通信的专用传输总线标准：MIL-STD-1553B。此总线全称是飞机内部时分制指令\响应式多路传输数据总线。本利用FPGA技术来实现此总线标准，保证能够正常收发信息，实现准确无误的通信。本采用的硬件平台是由ALTERA公司提供的DE2(Development and Education 2)开发板，板上集成的FPGA可编程芯片是EP2C35F672C6，属于Cyclone II系列。实现了通信收发电路设计、仿真，并下载到硬件上顺利通过测试。 关键字：FPGA技术；VHDL硬件描述语言；同步字头；奇校验 Abstract Integrated circuit(IC) technology recently has been divided two branches with the combination of modern computer technology and microelectronic technology. One is the traditional higher integration lever IC, the other is becoming popular technology by VHDL language, which is designed on the platform of field programmable gate array (FPGA). It can be made as the application specific integrated circuit (ASIC), which is named electronic design automation (EDA). Due to its low time cost and no consideration of made-IC process, FPGA has become the main method. So far, FPGA has been used widely in the field of communication, automatic controlling and signal processing. This article involves the data bus of MIL-STD-1553B in the military airplane. The mission is to guarantee the correctness of sent-signal or received-signal and communicate with no error by using FPGA. The method is proved to be correct and effective by using the ALTERA company’s FPGA programmable chip EP2C35F672C6 that belongs to CycloneII series which is integrated on the ALTERA Development and Education Board 2. Key words: FPGA technology; VHDL; synchronization; parity check 目 录 摘 要 Abstract 3 Key words: FPGA technology; VHDL; synchronization; parity check 3 1 1.1 课题背景 1 1.2 课题研究意义 2 1.3 课题研究目的 2 1.4 国内及国际研究现状 3 1.4.1 国内研究现状 3 1.4.2 国际研究现状 4 第二章 MIL-STD-1553B的帧结构及方案论证 7 2.1 MIL-STD-1553B总线的帧结构 7 2.2 关于MIL-STD-1553B实现的方案论证 7 第三章 FPGA的相关知识 11 3.1 EDA的发展历程 11 3.2 可编