2013年全国大学生电子设计竞赛简易频率特性测试仪(E).docVIP

2013年全国大学生电子设计竞赛 ） 【组】 2013年9月日FPGA和单片机为控制核心及数据处理核心，采用高分辨率DDS9854芯片产生1MHz-40MHz以0.1MHz为最小步进单位的任意频率正交扫描信号，其频率稳定度、幅度平衡误差、幅度平坦度及扫频时间均满足要求。通过精确的参数选择制作的RLC串联谐振电路其中心频率误差、有载品质因数、有载最大电压增益符合设计要求。利用零中频正交解调原理，经乘法器、低通滤波器、A/D转换后将信号送入FPGA控制模块运算得到被测RLC网络的幅频特性和相频特性数据，最终在液晶显示屏和示波器上同时显示幅频特性和相频特性数据及曲线。用键盘通过单片机控制系统设置点频、扫频步进和扫频频率范围，人机交互界面友好。报告中阐明了软硬件设计依据，给出了系统功能和性能测试结果Abstract This work is based on FPGA and single chip microcomputer as the control core and the data processing core, using high resolution DDS9854 chip generate 1MHz to 40MHz any frequency orthogonal scanning signal, whose smallest step unit is 0.1MHz. The frequency stability, amplitude balance error, amplitude flatness and frequency sweeping time are all satisfy the design requirements. Through choosing the precise parameters, produced the RLC series resonant circuit, whose center frequency error, loaded quality factor, loaded maximum voltage gain are all meet the design requirements. Using the zero if quadrature demodulation principle, make the signal through the multiplier, low pass filter, A/D conversion in turn, and then put it into the FPGA control module to calculate the amplitude frequency characteristic and the phase frequency characteristic data of the tested RLC network, finally show the amplitude frequency characteristic and phase frequency characteristic data and curve on both LCD screen and oscilloscope. Using the single chip controlled keyboard set point frequency, sweep frequency step and sweep frequency range, it also has friendly man-machine interface. The report describes the software and hardware design basis and relevant circuit, the test results of system function and performance are also presented. Keywords: Quadrature demodulation principle, sweep frequency, frequency characteristic tester, FPGA, DDS 目 录 1 方案比较与选择 1 1.1 扫频信号产生方案 1 1.2 相位检测方案 1 1.3 幅值检测 2 1.4 数据处理和控制系统选择 3 2 理论分析与计算 3 2.1 系统原理 3 2.2 RLC被测网络设计 4 2.3 正交解调原理 5 2.4 DDS信号源 6 3 电路与程序设计 6 3.1 椭圆滤波器设计 6 3.2 乘法器电路设计