基于FPGA的计算器设计毕业论文.doc

PAGE \* MERGEFORMAT PAGE \* MERGEFORMAT 0 PAGE \* MERGEFORMAT PAGE \* MERGEFORMAT 0 毕业设计（论文） 题目: 基于 FPGA 的计算器设计 The design of calculator based on FPGA  基于FPGA的计算器设计 研究生：XX 指导老师：XX 摘要 本文介绍了一个简单计算器的设计，基于硬件描述语言VHDL采用了现场可编程逻辑器件FPGA进行设计，并在Altera公司的Quartus Ⅱ软件上实现仿真。系统由键控模块、运算、存储模块和译码显示模块四个部分组成，计算部分为加法器、减法器、乘法器和除法器，存储部分需要3个存储器来实现：内部累加器（acc）、输入寄存器（reg）以及结果暂存器（ans）。显示部分由四个七段译码管组成，分别来显示输入数字，输入部分采用外接键盘，外部的8个按键他们能以单键和组合键的形式完成0~9999之内的 ‘加’、‘减’、‘乘’、‘除’、‘符号变换’、‘存储数据’和‘读取数据’等七种功能运算其结构简单，易于实现。 关键词:FPGA；VHDL；计算器；设计 The design of calculator based on FPGA Graduate Student: Dongdong Fan Supervisor: Shuxiang Song Abstract This article describes the design of a simple calculator, the design uses Field Programmable Gate Array FPGA based on VHDL hardware description language to design and Alteras Quartus Ⅱ in software for emulation. This system is componented by the key control module, computing, storage and decoding display module of the four parts, the computing part include adder, subtractor, multiplier and divider,Storage part needs three memory to help achieved: internal accumulator (acc), input register (reg) as well as the results of registers (ans). Display part is made up four decoder of 7 sections, respectively to show the number of input. The 8 keys they can by single combined key forms to be completed addition, multiplication, division arithmetic operator and symbol transform,stored data and read seven function of operation within 0 to 9999 numbers.its structure is simple and easy to implement. Key words：FPGA; VHDL; calclute ; design 目录 TOC \o 1-4 \h \u HYPERLINK \l _Toc21147 摘要 PAGEREF _Toc21147 I HYPERLINK \l _Toc9684 目录 PAGEREF _Toc9684 II HYPERLINK \l _Toc17003 第1章 引言 PAGEREF _Toc17003 1 HYPERLINK \l _Toc7381 1.1 课程设计的目的与意义 PAGEREF _Toc7381 1 HYPERLINK \l _Toc25655 1.2 国内外发展现状 PAGEREF _Toc25655 1 HYPERLINK \l _Toc5282 第2章FPGA技术及硬件描述语言 PAGEREF _Toc5282 2 HYPERLINK \l _Toc4191 2.1 EDA技术及其发展 PAGEREF _Toc4191 2 HYPERLINK \l _Toc21532 2.2