CSE 502 Graduate Computer Architecture Lec 12-13 –.pptVIP

CSE502-S11, Lec 12+13-Threads SMT CSE 502 Graduate Computer Architecture Lec 12-13 – Threading Simultaneous Multithreading Larry Wittie Computer Science, StonyBrook University /~cse502 and ~lw Slides adapted from David Patterson, UC-Berkeley cs252-s06 3/15-17/11 * CSE502-S11, Lec 12+13-Threads SMT 3/15-17/11 CSE502-S11, Lec 12+13-Threads SMT * Outline Thread Level Parallelism (from HP Chapter 3) Multithreading Simultaneous Multithreading Power 4 vs. Power 5 Head to Head: VLIW vs. Superscalar vs. SMT Commentary Conclusion Read Chapter 3 of Text Next Reading Assignment: Vector Appendix F 3/15-17/11 CSE502-S11, Lec 12+13-Threads SMT * Performance beyond single thread ILP ILP for arbitrary code is limited now to 3 to 6 issues/cycle, there can be much higher natural parallelism in some applications (e.g., database or scientific codes) Explicit (specified by compiler) Thread Level Parallelism or Data Level Parallelism Thread: a process with its own instructions and data (or much harder on compiler: carefully selected code segments in the same process that rarely interact) A thread may be one process that is part of a parallel program of multiple processes, or it may be an independent program Each thread has all the state (instructions, data, PC, register state, and so on) necessary to allow it to execute Data Level Parallelism: Perform identical (lock-step) operations on data when have lots of data. 3/15-17/11 CSE502-S11, Lec 12+13-Threads SMT * Thread Level Parallelism (TLP) ILP (last lectures) exploits implicitly parallel operations within a loop or straight-line code segment TLP is explicitly represented by the use of multiple threads of execution that are inherently parallel Goal: Use many instruction streams to improve Throughput of computers that run many programs Execution time of multi-threaded programs TLP could be more cost-effective to exploit than ILP for many applications. 3/15-17/11 CSE502-S11, Lec 12+13-Threads SMT * New Approach: Multit