数字电压表的Verilog程序.docVIP

//********************************************************* //** TLC549控制程序 //********************************************************* module TLC549(clk,reset,sdata,cs,adc_clk,data_out); input clk,reset,sdata; output cs,adc_clk; output [7:0]data_out; reg cs; reg [7:0]data_out; reg [7:0]data_out_r; reg [7:0]count_clk; reg adc_clk_r; reg clk_r; reg mark; //标识八位数据 reg flag ; //标识八位数据接收完 reg [3:0]cnt;//标识八位数的个数 parameter s0=0,s1=1,s2=2; reg [2:0]c_st; reg[5:0] temp; //1.4us 的计数 assign adc_clk=adc_clk_r; //assign adc_clk_r=~clk_r; always@(posedge clk) begin if (count_clk119) count_clk=count_clk+1; else begin count_clk=0;clk_r=~clk_r;end end always@(posedge clk) begin adc_clk_r=~clk_r; end always@(posedge clk_r or negedge reset) begin if (!reset) c_st=s0; else case (c_st) s0:begin cs=1;mark=0; if (temp==3) begin c_st=s1;temp=0;end else begin temp=temp+1;c_st=s0;end end s1:begin cs=0;mark=1; c_st=s2; end s2:begin cs=0;mark=1; if(flag==1)c_st=s0;else c_st=s2; end default:c_st=s0; endcase end always@(posedge adc_clk_r) begin if(mark==1) begin if(flag==1) data_out=data_out_r; else begin data_out_r={data_out_r[6:0],sdata};end end end always@(posedge adc_clk_r) begin if(mark==1) begin if(cnt==8) begin cnt=0;flag=1;end else begin cnt=cnt+1;flag=0;end end end endmodule //********************************************************* //** 10进制加法器 //********************************************************* module cnt10(V1,V2,q,c_in,c_out); input[3:0]V1,V2; input c_in; output [3:0]q; output c_out; reg [3:0]q; reg a,b; reg c_out; always@(V1,V2) begin if((V1[3:0]+V2[3:0]9)||((V1[3:0]=8)(V2[3:0]=8))||((V1[3:0]=9)(V2[3:0]=7))||((V1[3:0]=7)(V2[3:0]=9))) a=1; else a=0; if(V1[3:0]+V2[3:0]==9) b=1; else b=0; end always@(V1,V2,c_in,a) begin if(a==1c_in==1b==0) q[3:0]=V1[3:0]+V2[3:0]+7; else if(a==1c_in==0b==0) q[3:0]=V1[3:0]+V2[3: