CycloneV器件中收发器体系结构.PDF

Cyclone V器件中的收发器体系结构 1 2013.05.06 CV-53001 订阅 反馈 本章节介绍了Cyclone®V收发器体系结构、时钟、通道、通道绑定以及发送器和接收器通道数据通 路。 Altera®28-nm Cyclone V器件提供了速率为3.125Gbps和6.144Gbps的最低功耗的收发器。这些收发器 符合广泛的协议和数据速率标准；不过，6.144 Gbps仅支持公共无线电接口(CPRI)协议。 Cyclone V器件有多达12个串行数据速率在每秒614兆位(Mbps)和6.144 Gbps之间的收发器通道，并 且含有背板兼容的收发器支持PCI Express® (PCIe®) Base Specification 2.0 Gen1和Gen2多达x4 bonded 通道。 CycloneV收发器通道是全双工和基于时钟数据恢复(CDR)，带有物理编码子层((PCS)以及物理介质 附加子层((PMA)。 © 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at ISO /common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with 9001:2008 Alteras standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes Registered no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 101 Innovation Drive, San Jose, CA 95134 CV-53001 1-2 体系结构概述 2013.05.06 体系结构概述