MOS器件直流.pptVIP

* 工作区 NMOS PMOS 截止区 （VG-VT-VS）≤0 （VG-VT-VS≥0 线性区 （VG-VT-VS） 0 （VG-VT-VD） 0 （VG-VT-VS） 0 （VG-VT-VD） 0 饱和区 （VG-VT-VS） 0 （VG-VT-VD）≤0 （VG-VT-VS） 0（VG-VT-VD）≥0 * 长沟道MOS器件模型 3.1.1 MOS晶体管阈值电压分析 3.1.2 MOS晶体管电流方程 3.2.1 MOS晶体管的亚阈值电流 3.2.2 MOS晶体管的瞬态特性 3.2.3 MOS器件模型 * NMOS开关模型 Gate Source (of carriers) Drain (of carriers) | VGS | | VGS | | VT | | VGS | | VT | Open (off) (Gate = ‘0’) Closed (on) (Gate = ‘1’) Ron * 亚阈值区电流 亚阈值区 MOS表面弱反型 * 亚阈值电流特性 亚阈电流以载流子的扩散运动为主 弱反型的MOS表面相当于一个双极晶体管 * 亚阈值电流 亚阈电流随着栅压指数变化 当漏压大于3Vt的时候，亚阈电流基本与漏压无关 亚阈电流同温度强烈相关 * 亚阈值电流 * 亚阈值斜率 也称为亚阈摆幅（slew） * 温度对亚阈值斜率的影响 温度对亚阈值斜率的影响 体硅的亚阈值斜率一般不小于90mv/dec SOI器件的亚阈值斜率可以接近理论极限值60mv/dec SOI器件有更好的亚阈值特性 * * 阈值电压对截止态电流的影响 * The Power Crisis * 低功耗工艺 80 0.25 V 13,000 920/400 0.08 ?m 24 ? 1.2 V CL013 HS 52 0.29 V 1,800 860/370 0.11 ?m 29 ? 1.5 V CL015 HS 42 ? 42 ? 42 ? 42 ? Tox (effective) 43 14 22 30 FET Perf. (GHz) 0.40 V 0.73 V 0.63 V 0.42 V VTn 300 0.15 1.60 20 Ioff (leakage) (?A/?m) 780/360 320/130 500/180 600/260 IDSat (n/p) (?A/?m) 0.13 ?m 0.18 ?m 0.16 ?m 0.16 ?m Lgate 2 V 1.8 V 1.8 V 1.8 V Vdd CL018 HS CL018 ULP CL018 LP CL018 G From MPR, 2000 本节总结 MOS阈值电压 MOS导通电流 亚阈电流 * * Fourth terminal, body (bulk on previous slide) - substrate, not shown. Assumed connected to the appropriate supply rail, GND for NMOS, VDD for PMOS Electrons flow from source to drain – so current is referenced drain to source (IDS) Performs very well as a switch, little parasitic effects Today: STATIC (steady-state view) and later DYNAMIC (transient view) VGS 0.43 V for off VGS 0.43 V for on * Conductivity of the channel is modulated by the gate voltage - the larger the voltage difference between the gate and the source, the smaller the resistance of the conducting channel and the larger the current When VGS = 0 and the drain, source, and bulk are all connected to ground, the drain and source are connected by back-to-back pn-junctions (substrate-source and substrate-drain) - both are off (reverse biased)result