《基于FPGA的浮点运算器IP核的设计与实现》-毕业论文.doc

摘要 PAGE II l 基于FPGA的浮点运算器IP核的设计与实现 摘 要 浮点运算作为数字信号处理的最基本的运算，具备动态范围大的特点，不仅成为衡量微处理器性能的主要指标之一，而且广泛适用于复杂的数学计算、科学应用和工程设计中，随着多媒体技术的蓬勃发展，浮点运算单元的应用范围越来越广泛，它已经走入了千家万户，用来解决复杂的数字图像处理，移动物体模型的建立，三维动画设计与演示等等。随着FPGA的出现以及EDA技术的成熟，采用FPGA实现数字信号处理的方法已经显示出巨大的潜力，利用FPGA技术设计浮点乘法器可以缩短产品的开发周期。本设计提出了一种基于VHDL语言的浮点乘法器的硬件实现方法，就是用VHDL语言描述设计文件和原理图方式设计，以Altera公司的Cyclone系列产品为硬件平台，以Quartus为软件工具进行模拟仿真，实现了任意以IEEE754标准表示的23位单精度浮点数的乘法运算。设计中对阶码的溢出进行了研究并进行了处理，同时对结果进行了规格化处理，通过利用FPGA在线可编程的技术，设计出的浮点乘法器更加方便灵活，克服了专用乘法器的不足，更能广泛的应用到各个领域。 关键词：IEEE754，单精度浮点数，乘法器，硬件描述语言，FPGA，Quartus THE DESIGN AND IMPLEMENTATION OF FLOATING-POINT UNIT IP CORE BASED ON FPGA ABSTRACT As the most basic operation of digital signal processing, floating-point calculation is equipped with the characteristic of dynamic range, it is not only the main measure of microprocessor performance indexes, but also is widely used in complex mathematical calculation, science applications and engineering design. with the vigorous development of multimedia technology, floating point arithmetic unit has been widely used, and it has come home, been used to solve complex problems, such as digital image processing, the establishment of the moving object model, 3-d animation design and demonstrate, etc. With the maturity of FPGA presence and EDA technology, it has shown great potential to realize digital signal processing by the method of using FPGA, it can cut short the development cycle by using the FPGA technology design floating-point on time-multiplier. The design is proposed based on VHDL language of floating on time-multiplier, the hardware realization method is described with VHDL language schematic design documents and Altera design, by the way the Cyclone series products for hardware platform, with Quartus for software tools for simulation,it realized any twenty-three single precision floating-point multiplication which is in the IEEE754 standard. Design of order yards was studied and spill the processing, and the results are the normalized