基于SoC的加密IP核的测试系统设计与实现-微电子学与固体电子学专业论文.docxVIP

Abstract SoC technology in modern applications increasingly wide, more and more products are using this technology, it shortens the time to market of a product, saving the cost of the product design.SoC technology, however, is based on IP core reuse technology through the integration of proven IP cores together, to meet the design requirements. In the implementation process, the following work have been done, first by separate simulation of the main IP cores in the SoC including OR1200, Wishbone, UART, Ethernet,integration and debugging these IP core and writing assembly language, verify SoCfunction. Then use the built SoC functional verification of encrypted IP core AES, ECC, RSA encryption and decryption, and finally on the Xilinx the XC2VP30 development board do the FPGA verification. This article is unique in that, in the verification process using assembly language, assembly language has the advantages of short and pithy, easy to track, easy to debug. In the implementation process, the first thing is IP core integration and debugging, integrated CPU OR1200, Wishbone bus, clock module and BootROM/RAM, the UART to form the smallest debugging system and verify its functionality. Then added the Ethernet MAC core to the SoC system, composed of Ethernet debugging system, and verify functions SoC communication with PC via Ethernet. Followed by means of the above-built SoC system to verify the encryption IP core AES, ECC, RSA.Have done twice functional verification, the first in the minimum debugging system, verify encrypted IP core the functionof encrypt or decrypt; second in the Ethernet debugging system, verify SoC and host computer via Ethernet the encryption communication function. Finally,after the functional verification,we carry on FPGA verification.The tools used for Xilinx ISE 10.1.In the minimum debugging system, in the on-chip RAM provides encrypted data to encrypt IP core, transfer encrypt or decrypt data to a PC through the UART. In Ethernet debugging sy