基于VHDL的可编程逻辑器件虚拟实验平台的设计与实现-计算机技术专业论文.docxVIP

Abstract Virtual experiment means implementing a virtual experimental environment using multimedia technology, simulation technology, virtual reality technology and so on. It provides experimenters an interact way of experimental operation just like finishing a variety of experimental projects in real environment. It also provides experimenters operation experience similar to actual experimental practice, which has solved the problem of time limit, space limit as well as resource limit of traditional experiment teaching. The design and implementation of programmable logic device virtual experimental platform based on VHDL is discussed. A subset of VHDL is extracted for the virtual experiment platform by analyzing the synthesizable characteristic of VHDL language, and the scheme of programmable device virtual experiment platform based on VHDL is given. The platform includes 2 core modules: the VHDL code translation module and the simulation scheduling module. The core of the VHDL translation module is a VHDL compiler, which converts user-written VHDL source code to equivalent C++ language description and finally gets a number of corresponding C++ program files. Traditional event-driven simulation algorithm is studied and improved, used in dynamic scheduling of the translated C++ files, which achieves a dynamic behavior simulation of the static circuit description and finally generates a link library file. The simulation scheduling lib file is linked to the C++ files obtained by the translation module, then they are compiled, linked and built to a executable simulation program by C++ compiler. A B/S mode based virtual programmable logic device experimental platform is bulit using Flex Builder and VC++ on the basis of the scheme mentioned above. A specific example of experiment is done to test the platform. The result shows that the system has achieved the expected design requirements to establish the correct functional simulation model based on the input source