GPS接收机ADC关键元的研究与设计-微电子学与固体电子学专业毕业论文.docx

=|匕立变通厶堂亟±堂位论塞 =|匕立变通厶堂亟±堂位论塞 △垦曼!B△￡! AB STRACT ABSTRACT：With the development of GPS receiver in wireless communication system，the high performance analog—to—digital systems are demanded．ADC is the interface between analog signal and digital signal．In the GPS system，the analog signal coming from Mixer is transferred into digital signal，and then sent to Base band． Comparing with other most ADC architecture，the pipelined ADC can achieve high speed and high resolution．Furthermore，the number of comparators will be decreased， SO as to the area．Meanwhile，with the development of technology of IC，lower voltage and smaller mix—signal system is more important．In this design，we introduce the unit circuits of pipelined ADC whit 1．5 bit per stage． First，the Matlab．Simulink tool was used in ADC’S system level simulation，the model of pipelined ADC is established and proofed，the influence of offset voltage， offset capacitor and gain el ror to output range of pipelined stages was discussed，the high performance operational amplifier was employed in circuit design and capacitor matching was considered in layout design． Second．the circuit was designed in SMIC 0．1 8 pm mixed CMOS technology and stimulated by Cadence Specter in this paper．The analysis and design of S／H，subADC， MDAC were presented．Finally,the and layout and post simulation ar e shown in this paper． The flip-flop S／H circuit with the advantages of hi【gh gain and wideband of gain-boosting operation amplifier were used to achieve 1 0-bit，40MHz specifications required in the paper,the ideal of S／H was employed in the design of MDAC circuit， dynamic comparator was use in the design of sub ADC．The simulation results shown that the circuits meet the required specifications． KEYWORDS：A／D converter；Pipelined；Sample and hold；Comparator CLASSNO：TN79+2 学位论文版权使用授权书本学位论文作者完全了解北京交通大学有关保留、使用学位论文的规定。特 学位论文版权使用授权书 本学位论文作者完全了解北京交通大学有关保留、使用学位论文的规定。特 授权北京交通大学可以将学位论文的全部或部分内容编入有关数据库进行检索， 并采用影印、缩印或扫描等复制手段保存、汇编以供查阅和借阅。同意学校向国 家有关部门或机构送交