为紧凑型大批量应用实现可编程互连解决方案.PDF

A Lattice Semiconductor White Paper October 2014 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: (503) 268-8000 WP001 Introduction A new generation of compact, low power and low cost SERializer/DESerializer (SERDES) enhanced field programmable gate arrays (FPGAs) are increasingly being used with application specific integrated circuits (ASICs) and application specific standard products (ASSPs) by equipment designers to rapidly build flexible systems that meet tight cost, power and form factor constraints of many emerging high volume applications. These SERDES-enhanced FPGAs break the rule that FPGAs must be high density, power hungry and expensive having been optimized for low cost, small form factor and low power consumption, making them ideal for delivering programmable connectivity solutions to complement ASICs and ASSPs. To take advantage of SERDES-enhanced FPGAs’ unique capabilities, designers must understand a bit about how they work, as well as some of their thermal, electrical and signal integrity requirements. The material presented here is intended to familiarize you with this new breed of devices, the benefits they offer and introduce the design practices needed to successfully use them. Using FPGA family with embedded SERDES, it can introduce several important issues which can affect the performance of the SERDES- based device, and practical solutions which you can apply to your design. Most of the issues covered here will apply to the 3.25 Gbps SERDES transceiver cores found in many SERDES-enhanced FPGAs currently on the market, but it will also discuss some of the unique features Lattice h