时序电路设计和Verilog-浙江大学.ppt

数字系统设计@浙大数芯 * * ZDMC – Lec. #13 计数器 可预置的n位二进制计数器（带异步清0） module counter_n (out, cout, data, load, cin, clr, clk); parameter n = 8; output [n:1] out; output cout; input load, cin, clr, clk; input [n:1] data; reg [n:1] out; always @(posedge clk or negedge clr) //异步清0 begin if(!clr) out = 0; else if (load) out = data; //置数 else out = out + cin; //计数或保持 end assign cout = outcin; // 进位 endmodule CTR8 M1 M2 G3 C4/2,3+ 8 8 3CT=255 1,4D load cin clk data out cout clr R 计数器的位数 * ZDMC – Lec. #13 任意进制计数器（带异步清0） module n_counter (Q, CO, EN ,clr, clk); parameter n = 30; parameter size = 5; output [size : 1] Q; output CO; input EN, clr, clk; reg [size : 1] Q; always @(posedge clk or negedge clr) //异步清0 begin if(!clr) Q = 0; else if (Q == (n-1)) Q = EN ? 0 : Q; //计数或保持 else Q = Q + EN; //计数或保持 end assign CO = (Q == (n-1)) EN; // 进位 endmodule n:模；size：计数器位数 * ZDMC – Lec. #13 可预置的加减计数器 module up_down_count(d, clk, clear, load, up_down, qd); parameter size = 8; input[size:1] d; input clk, clear, load, up_down ; output[size:1] qd; reg[size:1] cnt; assign qd = cnt; always @(posedge clk) begin if(!clear) cnt = 0; //低电平、同步复位 else if(load) cnt = d; //高电平,同步置数 else if(up_down) cnt = cnt + 1; //加法计数 else cnt = cnt - 1; //减法计数 end endmodule CTR8 M1 M2 M3(dn) C5/ 8 8 1,4D load up_down clk d qd clr M4(up) 1,4+;1,3- 5CT=0 * ZDMC – Lec. #13 module count60(qout, cout, data, load, cin, reset, clk); parameter MODULUS = 8h23; output[7:0] qout; output cout; input[7:0] data; input load, cin, reset, clk; reg [7:0] qout; assign cout = (qout==MODULUS) cin; //进位 always @(posedge clk) begin if(reset) qout = 0; else if(load) qout = data;//同步置数 else