中值滤波器的VHDL设计.doc

PAGE 中值滤波器的VHDL设计 重庆邮电大学移通学院本科毕业设计（论文） 重庆邮电大学移通学院本科毕业设计（论文） 摘 要 随着超大规模集成电路(VLSI)技术的不断发展，图像的并行处理技术也得到飞速发展。现场可编程门阵列(FPGA)是在专用集成电路(ASIC)的基础上发展起来的一种可动态编程的器件，与其他中小规模集成电路相比，其优点主要在于它有很强的灵活性，即其内部的具体逻辑功能可以根据需要配置，对电路的修改和维护很方便，设计周期短，可重构，扩展性好等，特别适用于流水线方式的数据处理。 针对传统数字信号处理器件速度上的瓶颈问题，本文提出了一种基于FPGA 的快速中值滤波器设计方，对图像进行降噪处理。 本设计利用VHDL硬件描述语言为系统逻辑描述手段设计文件，在Quartus II软件环境下，采用自顶向下的设计方法，由各个基本模块共同构建了一个基于FPGA的中值滤波器，并在Modelsim下进行仿真。 系统以Altera公司ACEXlK系列的EPlKl00QC208-3型FPGA芯片为平台构建图像中值滤波实时处理模块，包括3×3模板生成模块、行列计数器模块、中值滤波模块、输入和输出模块。所编写的程序经编译和仿真，在可编程逻辑器件上下载验证，本系统能够很好的完成对图片椒盐噪声的滤除。 【关键词】数字图像处理 现场可编程门列阵（FPGA） VHDL 中值滤波器 ABSTRACT As VLSI circuits (VLSI) technology continues to develop, parallel processing technology has been rapid development of image. FPGA is in dedicated IC (ASIC) of Foundation Shang development up of a can dynamic programming of devices, and other small scale IC compared to, its advantages main is it has is strong of flexibility, is its internal of specific logic function can under needs configuration, on circuit of modified and maintenance is easy, design cycle short, can heavy frame, extended sexual good,, special applies Yu line way of data processing. Focusing on the speed problems of the traditional digital signal devices，a design of fast median filter based on FPGA was proposed in this paper for the Image noise reduction. This will use the hardware-description language VHDL description logic means for the system design documents, in Quartus II tools environment, a top-down design, by the various modules together build a FPGA-based media filter. And make the simulation under the environment of modelsim. The main system chips will use EPlKl00QC208-3,and make up of the Building modules of 3×3 template, the Counter module, modul of Media filter,and the module of input and output.At the last , compiling the design and simulation procedures,and the programmable logic device to download verification,this system can complete the picture of salt and pepper noise filter. 【Keywords】