A Low-Power Vector Processor Using Logarithmic Arithmetic for Handheld 3D Graphics Systems英文电子资料.pdf

A Low-Power Vector Processor Using Logarithmic Arithmetic for Handheld 3D Graphics Systems Byeong-Gyu Nam and Hoi-Jun Yoo Dept. of EECS, Korea Advanced Institute of Science and Technology (KAIST) 373-1, Guseong-dong, Yuseong-gu, Daejeon, 305-701, Republic of Korea Abstract - A low-power, high-performance 4-way 32-bit vector A. Number System processor is developed for handheld 3D graphics systems. It The proposed arithmetic unit is based on the hybrid contains a floating-point unified matrix, vector, and elementary approach of the FLP and the logarithmic number system function unit. By utilizing the logarithmic arithmetic, the unit (LNS) introduced in [4], where operations are reduced into achieves single-cycle throughput for all these operations except simpler ones in the LNS while the addition and subtraction are for the matrix-vector multiplication with 2-cycle throughput. The processor featured by this function unit, cascaded integer-float performed in FLP since the LNS addition and subtraction datapath, reconfiguration of datapath, operand forwarding in require nonlinear term evaluations. The logarithmic and logarithmic domain, and vertex cache takes 9.7mm2 in 0.18µm antilogarithmic converters between the FLP and the LNS are CMOS technology and achieves 141Mvertices/s for geometry proposed for this hybrid number system (HNS). transformation and 12.1Mvertices/s for OpenGL transformation