Altera可编程逻辑器件.pptVIP

Altera可编程逻辑器件 本章概要: Altera PLD器件系列 FPGA系列 Stratix II Stratix Cyclone II Cyclone Stratix II GX Stratix GX APEX II APEX 20K Excalibur Mercury FLEX 10K ACEX 1K FLEX 6000 FLEX 8000 CPLD系列 MAX II MAX 3000A MAX 7000 MAX 9000 CLASIC 器件系列简介: CPLD MAX II 系列特性 MAX II 应用 在一个单一器件内集成多个控制路径应用 器件系列简介:低成本FPGA Cyclone II 系列特性 Cyclone II 系列特性 器件系列简介:高密度FPGA Stratix II 系列特性 Stratix II 系列特性 Stratix II 系列特性 Cyclone系列 Cyclone系列特性 Cyclone系列特性 Cyclone系列器件结构 Cyclone器件主要由逻辑阵列块（LAB）、嵌入式存储器块、I/O单元和PLL等模块构成，在各个模块之间存在着丰富的互连线和时钟网络。 LAB Structure LAB Interconnects LAB Control Signals Logic Elements LE Operating Modes The Cyclone LE can operate in one of the following modes: Normal mode Dynamic arithmetic mode Normal Mode Dynamic Arithmetic Mode Carry-Select Chain MultiTrack Interconnect MultiTrack Interconnect MultiTrack Interconnect MultiTrack Interconnect Embedded Memory The Cyclone embedded memory consists of columns of M4K memory blocks. The M4K blocks support the following features: 4,608 RAM bits 200 MHz performance True dual-port memory Simple dual-port memory Single-port memory Byte enable Parity bits Shift register FIFO buffer ROM Mixed clock mode Memory Modes Memory Modes Shift Register Memory Configuration Sizes Memory Configuration Sizes Byte Enables Control Signals M4K Interface Control Signals M4K Interface Independent Clock Mode Input/Output Clock Mode Input/Output Clock Mode Read/Write Clock Mode Single-Port Mode Global Clock Network Combined Resources Combined Resources PLLs PLLs PLLs I/O Structure IOEs support many features, including: ■ Differential and single-ended I/O standards ■ 3.3-V, 64- and 32-bit, 66- and 33-MHz PCI compliance ■ Joint Test Action Group (JTAG) boundary-scan test (BST) support ■ Output drive strength control ■ Weak pull-up resistors during configuration ■ Slew-rate control ■ Tri-state buffers ■ Bus-hold circuitry ■ Programmable pull-up resistors in user mode ■ Programmable input and output delays ■ Open-drain outputs ■