CPUFPGA混合架构上的硬件线程加速方法-浙江大学计算机学院.PDF

ISSN 1000-9825, CODEN RUXUEW E-mail: jos@ Journal of Software , Vol.20, Supplement, December 2009, pp.15−22 © by Institute of Software , the Chinese Academy of Sciences . All rights reserved. Tel/Fax: +86-10 ∗ CPU/FPGA混合架构上的硬件线程加速方法 + 陈天洲 , 严力科, 胡 威, 马吉军 (浙江大学 计算机科学与技术学院,浙江 杭州 310027) Hardware Thread Accelerating Method Based on CPU/FPGA Hybrid Architecture + CHEN Tian-Zhou , YAN Li-Ke, HU Wei, MA Ji-Jun (College of Computer Science, Zhejiang University, Hangzhou 310027, China) + Corresponding author: E-mail: tzchen@ Chen TZ, Yan LK, Hu W, Ma JJ. Hardware thread accelerating method based on CPU/FPGA hybrid architecture. Journal of Software, 2009,20(Suppl.):15−22. /1000-9825/09003.htm Abstract : The CPU/FPGA hybrid architecture is a popular reconfigurable computing architecture. In order to ease the use of FPGA, a hardware thread approach is proposed, and a hardware thread executing mechanism is designed to make use of the reconfigurable resources. Software thread and hardware thread can be executed in parallel while computation-intensive tasks are assigned to hardware threads and control-intensive tasks are assigned to software threads. Simics simulator is adopted to simulate a hybrid architecture platform, on which software and hardware multithreading DES, MD5SUM and MergeSort algorithms are evaluated. The results show that the average speedup is 2.30, and it proves that the approach explored the performance of CPU/FPGA hybrid architecture efficiently. Key words : hardware acceleration; hardware thread; multithreading; CPU/FPGA hybrid architecture; reconfigurable computing 摘 要: CPU/FPGA 混合架构是可重构计算的普遍结构,为了简化混合架构上FPGA 的使用,提