采利用集成FPGA设计流程优化电机控制设计.pdf

FPGA WP-01162-1.2 ® Model Optimize Compile Chip Algorithm Implementation Integrate Design Placement MATLAB/Simulink DSP Builder SOPC Builder/Qsys Quartus II ● Model System ● Optimize Algorithm ● System Integration ● HDL Synthesis ● Develop ● Logic Folding ● Embedded ● Fitting FPGA Algorithm ● Floating and Processors ● Program File Fixed Point ● Networking and Generation ● DSP Block HDL Interface IP Output ■ ■ ■ ■ © 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at /common/legal.html. Altera warrants performance of its 101 Innovation Drive semiconductor products to current specifications in accordance with Alteras standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the