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FILENAME 数字式秒表
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《电子技术》课程设计报告
题 目 数字式秒表
指导教师(签字)
目录
摘要··················································4
关键字················································4
技术要求··············································4
系统综述··············································4
系统框图··············································5
总图··················································6
单元电路设计··········································7
时钟脉冲发生电路··············································7
计数电路······················································8
译码器························································9
控制电路······················································11
闹钟定时报警··················································13
闹钟预置数(定时)模块···········································13
预置,实际时间对比模块···········································14
时间比较模块·····················································14
报警模块·························································15
总结·····················································16
参考文献················································16
鸣谢····················································17
收获与体会··············································17
元器件列表··············································18
数字式秒表
摘要
该数字计数系统的逻辑结构较简单,是由控制电路,复位电路,0.01秒脉冲发生器,译码显示电路构成的。利用555构建多谐振荡器,产生频率为100Hz的时钟脉冲。结合74LS160的功能利用J1和J2两个功能开关实现秒表的计数、暂停、清零功能。
关键词 计数器,译码器,显示器,555定时器构成的多谐振荡器
技术要求
秒表最大计时值为99分59.99秒;
6位数码管显示,分辨率为0.01秒;
具有清零、启动计时、暂停及继续计数等控制功能;
控制操作键不超过二个。
一、系统综述
本计时器由时钟脉冲发生电路、加计数器电路、译码电路和数码管显示器几大部分构成。利用555构建多谐振荡器,产生频率为100Hz的时钟脉冲,以满足精确到0.01s的课题要求。加计数器构成计时器的分位、秒位和毫秒位。除秒位采取60进制,其余采取100进制故选用74LS160。显示部分用译码器配合数码管构成。结合74LS160的功能利用J1和J2两个功能开关实现秒表的计数、暂停、清零功能。
为增强该数字秒表的实用性能。特添加定时功能和整点报警功能,但在该报告中不予以重点论述。
方案论证及误差分析
方案论证详述
一:振荡器作为数字式秒表的基础核心,产生一个频率标准,其精度与稳定度基本决定了秒表的计时准确度和精度。其所产生的精度影响将影响到整个数字式秒表的成败。故在振荡器的选择上应当特别注意
1.振荡器的方案选择:
方案一:集成时钟芯片.
计划使用DS1302 来作为所需的集成时钟芯片. DS1302是 HYPERLINK /view/2398.htm \t _blank
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