2PSK2DPSK数字信号频带传输系统的设计与建模.docVIP

PSK调制电路的建模 library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity PL_CPSK is port(clk:in std_logic; start:in std_logic; x:in std_logic; y:out std_logic); end PL_CPSK; architecture behav of PL_CPSK is signal q:std_logic_vector(1 downto 0); signal f1,f2:std_logic; begin process(clk) begin if clkevent and clk=1 then if start=0 then q=00; elsif q=01 then f1=1;f2=0;q=q+1; elsif q=11 then f1=0;f2=1;q=00; else f1=0;f2=1;q=q+1; end if; end if; end process; process(clk,x) begin if clkevent and clk=1 then if q(0)=1 then if x=1 then y=f1; else y=f2; end if; end if; end if; end process; end behav; 2．CPSK解调 library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity PL_CPSK2 is port(clk:in std_logic; start:in std_logic; x:in std_logic; y:out std_logic); end PL_CPSK2; architecture behav of PL_CPSK2 is signal q:integer range 0 to 3; begin process(clk) begin if clkevent and clk=1 then if start=0 then q=0; elsif q=0 then q=q+1; if x=1 then y=1; else y=0; end if; elsif q=3 then q=0; else q=q+1; end if; end if; end process; end behav; DPSK调制 绝对码到相对码 library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity PL_DPSK is port(clk:in std_logic; start:in std_logic; x:in std_logic; y:out std_logic); end PL_DPSK; architecture behav of PL_DPSK is signal q:integer range 0 to 3; signal xx:std_logic; begin process(clk,x) begin if clkevent and clk=1 then if start=0 then q=0;xx=0; elsif q=0 then q=1;xx=xx xor x;y=xx xor x; elsif q=3 then q=0; else q=q+1; end if; end if; end process; end behav; 4．DPSK解调 相对码到绝对码 library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity PL_DPSK2 is port(clk:in std_logic; start:in std_logic; x:in std_logic; y:out std_logic)