脉冲宽度测量仪毕业设计说明书.doc

PAGE 英文摘要 毕业设计说明书 题目：脉冲宽度测量仪设计 学生姓名： 李敬阳 学号： 0705014141 学 院： 信息与通信工程学院 专 业： 电子信息科学与技术 指导教师： 李建民 2011年 6 月 中文摘要 第 PAGE I页 共Ⅳ页 中文摘要 脉冲宽度测量仪设计 摘要：随着电子技术的发展，当前数字系统的设计正朝着速度快、容量大、体积小、重量轻的方向发展。然而，使用传统的数字系统设计方法来设计脉冲宽度测量系统需要在电路板上进行，此方法电路复杂、调试困难、错误查找和修改不便、可移植性差、产品开发周期长，针对此种情况本文介绍了一种自顶向下、分层设计的脉冲宽度测量仪的设计方法。 该测量仪采用VHDL硬件描述语言进行编程，并以MAX+PLUSⅡ为开发环境，极大地减少了硬件资源的占用，且该脉冲测量仪的模块划分具有相对独立性，可以对模块单独进行设计、调试和修改，缩短了设计周期。本次设计的脉冲宽度测量仪要求测量脉冲的宽度和频率，脉冲宽度测量范围为50us—50ms，其测试结果由4只数码管显示。与传统方法做成的脉冲宽度测量仪相比，该测量仪具有体积小，可靠性高，灵活性强等特点。仿真波形与分析结果表明，所设计的电路通过硬件仿真能够满足脉冲宽度测量仪的功能要求，具有理论与实践意义，实现了电子设计自动化的过程。 关键词：脉冲宽度，EDA仿真，VHDL 英文摘要 第 PAGE III页 共Ⅳ页 英文摘要 The Design of Pulse Width Measuring Instrument Abstract：With the development of electronic technology, the current design of digital systems is moving to the direction of fast speed, large capacity, small size and light weight. However, traditional methods of digital system design used to design pulse width measurement system must run in the circuit board, which is difficult in many ways, for example, complex circuit, difficult debugging, the inconvenience of error searching and modifying, poor portability, long development cycle. For that reason, this article describes a top-down, hierarchical design of pulse width measuring instrument. The measuring instrument uses VHDL hardware description language to programme,taking MAX+PLUSⅡas the environment of the development, which greatly reduces the occupation of the hardware resources, and the module can be designed ,debugged and modified separately as a result of the relatively independent module of the pulse measuring instrument , which will shorten the design cycle. The design attaches importance to the measurement of pulse width and period measurement, ranging from 50us to 50ms, whose test results will display with four digital pipes. Compared to the pulse width measuring instrument made with traditional methods, the characteristics of the measuring instrume