chap2-new微机电构装系统汇编.ppt

Flip Chip 2nd level packaging IC packages can be classified two categories: 1. through-hole 2. surface mount These two categories refer to the methodology used in assembly the package the printed wiring board (PWB) Classification of IC Packaging Pin-Through-Hole (PTH) Packaging versus Surface Mount Technology (SMT) Packaging Through-Hole If the package have pins that can be inserted into holes in the PWB, they are called through-hole packages. Surface mount If the package are not inserted into the PWB, but are mounted on the surface, of the PWB, they are called surface mount packages. From Through-hole to Surface Mount 2nd level packaging SMT-Surface Mount Technology BGA 3rd level and higher packaging The advantage of the surface mount package, as compared to through-hole, is that both sides of the PWB can be used, and therefore, higher packaging density can be achieved on the board . CSP The CSP, definition , is a package whose Area is less than 1.2 times the area of IC it packages . CSP THE ROLE OF PACKAGING IN MICROELECTRONICS CHAPTER　2 電子構裝技術 電子構裝技術 The Role of Packaging Different functional roles: - Power distribution: supply power current to devices/chips - Signal distribution: connecting electrical and optical signals from chip to chip or to external devices - Heat dissipation: remove heat from the devices/chips, make system reliable - Package protection: protect devices or chips from environmental or mechanical damages The Role of Packaging 積體電路製程最重要的步驟，有以下七項。 (l) 單晶成長 (2) 生成矽晶薄膜 (3) 生成絕緣層 (4) 微影蝕刻形成電路圖形　 (5) 摻入電活性雜質及熱處理 　 (6) 製作金屬接面及連線 (7) 切片與構裝 積體電路製程 (1)單晶成長 柴氏拉升法示意圖 矽單晶棒晶元 (4) 微影蝕刻形成電路 圖形 蝕刻形成電路圖形步驟 (2) 生成矽晶薄膜 (3) 生成絕緣層 (5) 摻入電活性雜質及熱處理 離子佈值示意圖 熱處理後佈值之離子於擴散重新分佈 (6) 製作金屬接面及連線 ?蒸鍍於二氧化矽開口之金屬薄膜(掃描式電子顯微鏡像) 線接面上金屬矽化物層模截面示意圖 (7) 切片與構裝 IC: integrated circuit SSI: small scale integration MSI: medium scale integration LSI: large scale integration VLSI: very large scale integration ULSI: ultra scale integrati