集成电路工艺和版图设计(参考).ppt

Jian Fang Jian Fang 集成电路工艺和版图设计概述Jian FangIC Design Center, UESTC 微电子制造工艺 版图设计（layout）及相关技术 Cell development (Analog/digital)Analog design Schematic entry (transistor symbols) Analog simulation (SPICE models) Layout (layer definitions) Design Rule Checking, DRC ( design rules) Extraction (extraction rules and parameters) Electrical Rule Checking, ERC (ERC rules) Layout Versus Schematic, LVS ( LVS rules) Layout Drawing geometrical shapes: Defines layout hierarchy Defines layer masks Requires detailed knowledge about CMOS technology Requires detailed knowledge about design rules (hundreds of rules) Requires detailed knowledge about circuit design Slow and tedious Optimum performance can be obtained Digital design Behavioral simulation ……………….. Simulation/timing verification with estimated back-annotation Place and route (place and route rules) Design Rule Check, DRC (DRC rules) Loading extraction (rules and parameters) Simulation/timing verification with real back-annotation Design export ……………………….. Place and Route Generates final chip from gate level netlist Goals: Minimum chip size Maximum chip speed. Placement: Placing all gates to minimize distance between connected gates Floor planning tool using design hierarchy Specialized algorithms ( min cut, simulated annealing, etc.) Timing driven Manual intervention Very compute intensive Routing: Channel based: Routing only in channels between gates  (few metal layers: 2) Channel less: Routing over gates (many metal layers: 3 - 6) Often split in two steps: Global route: Find a coarse route depending on local routing density Detailed route: Generate routing layout Performance of sub-micron CMOS IC’s are to a large extent determined by place route. Loading delays bigger than intrinsic gate delays Wire R-C delays becomes important in sub-micron Clock distribution over complete chip gets critical at operating frequencies