lect10-时序电路设计.ppt

* * * * * * * 11: Sequential Circuits * Two-Phase Clocking If setup times are violated, reduce clock speed If hold times are violated, chip fails at any speed In this class, working chips are most important No tools to analyze clock skew An easy way to guarantee hold times is to use 2-phase latches with big nonoverlap times Call these clocks f1, f2 (ph1, ph2) 11: Sequential Circuits * Safe Flip-Flop Past years used flip-flop with nonoverlapping clocks Slow – nonoverlap adds to setup time But no hold times In industry, use a better timing analyzer Add buffers to slow signals if hold time is at risk 11: Sequential Circuits * Adaptive Sequencing Designers include timing margin Voltage Temperature Process variation Data dependency Tool inaccuracies Alternative: run faster and check for near failures Idea introduced as “Razor” Increase frequency until at the verge of error Can reduce cycle time by ~30% 11: Sequential Circuits * Summary Flip-Flops: Very easy to use, supported by all tools 2-Phase Transparent Latches: Lots of skew tolerance and time borrowing Pulsed Latches: Fast, some skew tol borrow, hold time risk * * * * * * * * * * * * * * * * * * * * * * * * * * * * 11: Sequential Circuits CMOS VLSI Design CMOS VLSI Design 4th Ed. Lecture 11: Sequential Circuit Design 11: Sequential Circuits * Outline Sequencing Sequencing Element Design Max and Min-Delay Clock Skew Time Borrowing Two-Phase Clocking 11: Sequential Circuits * Sequencing Combinational logic output depends on current inputs Sequential logic output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline 11: Sequential Circuits * Sequencing Cont. If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Ex: fiber-optic cable Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses T