lect9-组合电路设计课件.ppt

* * * * * * * * * 10: Combinational Circuits CMOS VLSI Design CMOS VLSI Design 4th Ed. Lecture 9: Combinational Circuit Design 10: Combinational Circuits * Outline Bubble Pushing Compound Gates Logical Effort Example Input Ordering Asymmetric Gates Skewed Gates Best P/N ratio 10: Combinational Circuits * Example 1 module mux(input s, d0, d1, output y); assign y = s ? d1 : d0; endmodule 1) Sketch a design using AND, OR, and NOT gates. 10: Combinational Circuits * Example 2 2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available. 10: Combinational Circuits * Bubble Pushing Start with network of AND / OR gates Convert to NAND / NOR + inverters Push bubbles around to simplify logic Remember DeMorgan’s Law 10: Combinational Circuits * Example 3 3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available. 10: Combinational Circuits * Compound Gates Logical Effort of compound gates 10: Combinational Circuits * Example 4 The multiplexer has a maximum input capacitance of 16 units on each input. It must drive a load of 160 units. Estimate the delay of the two designs. H = 160 / 16 = 10 B = 1 N = 2 10: Combinational Circuits * Example 5 Annotate your designs with transistor sizes that achieve this delay. 10: Combinational Circuits * Input Order Our parasitic delay model was too simple Calculate parasitic delay for Y falling If A arrives latest? 2t If B arrives latest? 2.33t 10: Combinational Circuits * Inner Outer Inputs Inner input is closest to output (A) Outer input is closest to rail (B) If input arrival time is known Connect latest input to inner terminal 10: Combinational Circuits * Asymmetric Gates Asymmetric gates favor one input over another Ex: suppose input A of a NAND gate is most critical Use smaller transistor on A (less capacitance) Boost size of noncritical input So total resistance is same gA = 10/9 gB = 2 gtotal = gA + gB = 28/9 Asymmetric gate approaches g = 1 on critical input But total