chapter6problems（全英文版设置）.pdf

1 Chapter 6 Problem Set Chapter 6 PROBLEMS 1. [E, None, 4.2] Implement the equation X = ((A + B) (C + D + E) + F) G using complemen- tary CMOS. Size the devices so that the output resistance is the same as that of an inverter with an NMOS W/L = 2 and PMOS W/L = 6. Which input pattern(s) would give the worst and best equivalent pull-up or pull-down resistance? Solution Rewriting the output expression in the form X = ((A + B) (C + D + E) + F) G = ((AB + CDE)F) + G allows us to build the pulldown network by inspection (parallel devices imple- ment an OR, and series devices implement an AND). The pullup network is the dual of the pulldown network. A B 24 24 F 12 C D E 24 24 24 G 12 X A 8 C 12 G 2 B D 8 12 E 12 F 4 The plot shows sizes that meet the requirement - in the worst case, the output resistance of the circuit matches the output resistance of an inverter with NMOS W/L=2 and PMO