eda技术与vhdl vhdl状态机.pptxVIP

EDA技术与VHDL ;5.1 状态机设计相关语句 ;5.1 状态机设计相关语句 ;5.1 状态机设计相关语句 ;5.1 状态机设计相关语句 ;5.1 状态机设计相关语句 ;5.1 状态机设计相关语句 ;【例5-1】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY s_machine IS PORT ( clk,reset : IN STD_LOGIC; state_inputs : IN STD_LOGIC_VECTOR (0 TO 1); comb_outputs : OUT INTEGER RANGE 0 TO 15 ); END s_machine; ARCHITECTURE behv OF s_machine IS TYPE FSM_ST IS (s0, s1, s2, s3); --数据类型定义，状态符号化 SIGNAL current_state, next_state: FSM_ST;--将现态和次态定义为新的数据类型 BEGIN REG: PROCESS (reset,clk) --主控时序进程 BEGIN IF reset = 1 THEN current_state = s0;--检测异步复位信号 ELSIF clk=1 AND clkEVENT THEN current_state = next_state; END IF; END PROCESS; COM:PROCESS(current_state, state_Inputs) --主控组合进程 （接下页）;BEGIN CASE current_state IS WHEN s0 = comb_outputs= 5; IF state_inputs = 00 THEN next_state=s0; ELSE next_state=s1; END IF; WHEN s1 = comb_outputs= 8; IF state_inputs = 00 THEN next_state=s1; ELSE next_state=s2; END IF; WHEN s2 = comb_outputs= 12; IF state_inputs = 11 THEN next_state = s0; ELSE next_state = s3; END IF; WHEN s3 = comb_outputs = 14; IF state_inputs = 11 THEN next_state = s3; ELSE next_state = s0; END IF; END case; END PROCESS; END behv; ;5.1 状态机设计相关语句 ;5.2 Moore状态机 ;5.2 Moore状态机 ;5.2 Moore状态机 ;【例5-2】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ADCINT IS PORT(D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);--来自0809转换好的8位数据 CLK : IN STD_LOGIC; --状态机工作时钟 EOC : IN STD_LOGIC; --转换状态指示，低电平表示正在转换 ALE : OUT STD_LOGIC; --8个模拟信号通道地址锁存信号 START : OUT STD_LOGIC; --转换开始信号 OE : OUT STD_LOGIC; --数据??出3态控制信号 ADDA : OUT STD_LOGIC; --信号通道最低位控制信号