亚诺德半导体资料ISSCC2020-16_Digest (1).pdfVIP

ISSCC 2020 / SESSION 16 / NYQUIST VCO-BASED ADCs / OVERVIEW Session 16 Overview: Nyquist VCO-Based ADCs DATA CONVERTERS SUBCOMMITTEE Session Chair: Bob Verbruggen Session Co-Chair: Takashi Oshima Xilinx, Dublin, Ireland Hitachi, Tokyo, Japan Subcommittee Chair: Michael Flynn, University of Michigan at Ann Arbor, Ann Arbor, MI This session highlights the latest developments in Nyquist and VCO-based ADCs. These ADCs use innovative architectures and techniques to improve speed, linearity or power consumption. Three designs with GHz bandwidth, two SAR-based designs with tens of MHz of bandwidth and two VCO-based designs offer an interesting mix of architectures and applications. Several designs also attempt to tackle the challenge of driving the ADC, using track-and-hold amplifiers, input capacitance reduction, or inherent anti-aliasing. 1:30 PM 16.1 A 12b 18GS/s RF Sampling ADC with an Integrated Wideband Track-and-Hold Amplifier and Background Calibration A. M. A. Ali, Analog Devices, Greensboro, NC In Paper 16.1, Analog Devices presents a 16nm design that achieves a record 18GS/s with 50 dB linearity. It achieves 48dB SNDR and 54dB SFDR for an 8GHz signal sampled at 18GS/s. This performance is enabled by a wideband track-and-hold amplifier and extensive background calibration. 2:00 PM 16.2 A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving 37.5dB SNDR at 18GHz Input