基于ROM结构的温度计码解码器设计说明书.docx

基于 ROM 结构的温度计码解码器的设计 摘 要：可以实现皮秒级别测量精度的时间数字转换器广泛用于激光测距、高能物理和航空通信等场合。时间数字转换器主要由延时链、锁存延时链输出的寄存器组和解码器组成。利用 FPGA 实现时间数字转换器与开发时间数字转换器集成芯片相比具有开发周期短、实现容易、外围电路简单、系统集成度高和升级简单等优点。 温度计码解码器是时间数字转换器的关键电路，它决定了转换器连续工作的最大频率，决定了转换器系统电路的资源使用，决定了单片 FPGA 内容纳时间数字转换器通道的个数，决定了转换器对亚稳态造成的温度计码中的“气泡”的抑制能力。设计采用模/数转换器设计中的 ROM 结构的温度计码解码器。针对 EP3C10E144C7 的 4 输入查找表结构，从 4、8、16 输入的温度计码解码器的逻辑表达式入手，推演处应用于任意位温度计码解码器的通用公式，并成功实现了 32、64、128、256、512 位温度计码的解码。基于 FPGA 的 ROM 结构的解码器电路由把温度计码转换为1-out-of-n 码的预处理电路和以或运算为核心的非常适于 FPGA 查找表结构的解码电路构成。其中预处理电路可以消去温度计码中 2 个以内的“气泡”误差。解码器最 大工作频率随着温度计码位数的增加而降低，512 位温度计码解码时间小于 7 ns。 关键词：FPGA；温度计码；解码器；ROM 结构 The design of the thermometer code decoder based on the ROM structure Abstract：The time to digital converter (TDC) with the picosecond-level measurement can be widely used in laser ranging, high energy physics and aviation communication.. It is composed of the register group which latches the outputs of the delay chain and the decoder. Comparing with development time to digital converter chip, Using FPGA to realize the time to digital converter has the advantages of short development cycle, easy realization, simple peripheral circuits, the high degree of system integration and simple upgrading. Thermometer decoder is the key circuit of TDC, which limits the maximum frequency of TDC in continuous working, decides the using resource of converter circuit, determines the number of TDC channel in a single FPGA, decides the inhibition ability of the bubble of the thermometer code which caused by the metastable state. The design uses ROM structure decoder of the analog/digital converter. For four input lookup table structure of EP3C10E144C7, beginning from the logic expressions of 4, 8, 16 input thermometer decoder, the design derives the general formula of the arbitrary bit thermometer decoder, and the successful achieves the 32, 64, 128, 256, 512 bit thermometer code decoding. Based on FPGA the decoder circuit of the ROM structure is composed of the preprocessing circuit which