verilog语言编写的跑表器.docVIP

设计：本设计是用verilog语言编写的跑表器，有百分秒位，秒位，分位，用六个led7段显示，输入的时钟频率是50Mhz,CLR为低时开始计数为高时复位，PAUSE位高时计数为低时暂停。CLR和PAUSE可以用按键控制。按键正常态位1按下位0。仿真时间较长但能实现功能，请读者自行仿真结果。 hezhi100源程序 module hezhi100(clk,clr,clk_out); input clk,clr; output clk_out; reg clk_out; reg[18:0] count; always @(posedge clk ) begin if(clr==0) begin if(count==250000) begin clk_out=~clk_out;count=0;end else count=count+1; end else count=0; end endmodule fenmiaojishu源程序 module fenmiaojishu(CLK,CLR,PAUSE,MSH,MSL,SH,SL,MH,ML); input CLK; input CLR; input PAUSE; output[3:0] MSH,MSL; output[3:0] SH,SL; output[3:0] MH,ML; reg[3:0] MSH,MSL; reg[3:0] SH,SL; reg[3:0] MH,ML; reg cn1,cn2;//cn1为百分秒向秒的进位，cn2为秒向分的进位 //百分秒计数进程，每计满100，cn1产生一个进位 always @(negedge CLK) begin if(CLR) begin MSH=0;MSL=0; end else if(PAUSE) begin if(MSL==9) begin MSL=0; if(MSH==9) begin MSH=0;cn1=1; end else MSH=MSH+1; end else begin MSL=MSL+1;cn1=0; end end end //秒计数进程,每计满60,cn2产生一个进位 always @(posedge cn1) begin if(CLR) begin SH=0;SL=0; end else if(SL==9) begin SL=0; if(SH==5) begin SH=0;cn2=1; end else SH=SH+1; end else begin SL=SL+1;cn2=0; end end //分计数进程,每计满60,系统自动清零 always @(posedge cn2) begin if(CLR) begin MH=0;ML=0; end else if(ML==9) begin ML=0; if(MH==5) MH=0; else MH=MH+1; end else ML=ML+1; end endmodule trlcom源程序（生成led的片选信号低电平有效） module trlcom(clr,com); input clr; output[5:0] com; reg[5:0] com; always if(clr==1) begin com=6b111111;end else com=0; endmodule led7源程序 module led7(out,data); input[3:0] data; //7段显示器输入 output[6:0] out; //7段显示器字段输出 reg[6:0] out; always @(data) case(data) 4d0: out = 7b1000000; 4d1: out = 7b1111001; 4d2: out = 7b0100100; 4d3: out = 7b0110000; 4d4: out = 7b0011001; 4d5: out = 7b0010010; 4d6: out = 7b0000010; 4d7: out = 7b1111000; 4d8: out = 7b0000000; 4d9: out = 7b0010000; default:out = 7b1111111; //当data为4hA~4hF时，七段显示器不亮 endcase endmodule 仿真前的输入波形设置