VHDL用pwm生成函数信号.docVIP

library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.std_logic_arith.all; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity zuoye is PORT( clk : IN STD_LOGIC;--时钟信号 led : out std_logic;--亮灯信号 num2 : IN STD_LOGIC; --频率选定 num1 : IN STD_LOGIC; --波形选择 smg : out std_logic_vector(6 downto 0); --数码管的段数据 smgkz : out std_logic_vector(3 downto 0); --数码管的选通信号 pwm_out:out std_logic ); END zuoye; architecture boxing of zuoye is signal k:integer range 0 to 3; signal m:integer range 1 to 3:=1; signal clk1k,clk1:std_logic; signal count:integer range 1 to 25000:=1; signal key3filt : std_logic; --按键change消抖后得到的信号 signal key3cnt : integer range 0 to --用于对yiwei按键输入有效时间进行计数 signal key4filt : std_logic; --按键yiwei消抖后得到的信号 signal key4cnt : integer range 0 to --用于对CHANGE按键输入有效时间进行计数 signal pin:integer range 1 to 3:=1; signal counta,countb,countc,countd,counte,countf,countg,counth,counti:integer range 0 to signal counta1,countb1,countc1,countd1,counte1,countf1,countg1,counth1,counti1:integer range 0 to signal out1,out2,out3,out4,out5,out6,out7,out8,out9:std_logic; signal aa,ab,ac:integer:=0; signal c1,c2,c3:integer range 0 to --按键消抖 Begin process (num1)---num1 constant N :integer := 5000000; begin if clkevent and clk = 1 then if num1 = 0 then --当key1 输入低电平，即按键按下 if key3cnt /= N then --一直计数到N key3cnt = key3cnt + 1; end if; if key3cnt = N-1 then --最后一个计数时输出key1filt脉冲 key3filt = 1; else key3filt = 0; end if; else key3cnt = 0; end if; end if; end process; process (num2)---num2——消抖 constant N :integer := 5000000; begin if clkevent and clk = 1 then if num2 = 0 then if key4cnt /= N then key4cnt = key4cnt + 1; end if; if key4cnt = N-1 then key4filt = 1; else key4filt = 0; end if; else key4cnt = 0; end if; end if; end process; process(clk) begin if (clkevent and clk=1) then if