芯片-封装-系统热完整性协同分析.ppt

Chip Package System (CPS) Thermal Integrity Co-Analysis Chip-Package-System Thermal Integrity Solution IC Simulation for Thermal-aware EM ( RedHawk/Totem ) Chip-aware package and system thermal analysis CTMs Temperature Map 3D IC Package Simulation CTA Converged Power Map Thermal BC System-aware package and chip thermal and Thermal-aware EM analysis System Simulation ( Icepak ) 2 ? 2017 ANSYS, Inc. August 3, 2017 ANSYS UGM 2017 Chip Board Aware Package Level Thermal Analysis Chip data Pkg data PrototypedBC JEDEC Board Info HTC (Heat TransferCoefficient) OR Redhawk-CTA System data Pkg data ? JEDEC board is widely used for easy package level analysis when info about system is not ready or explicit 3 ? 2017 ANSYS, Inc. August 3, 2017 ANSYS UGM 2017 Chip Thermal Model (CTM) from RH/Totem Layer stackup Power (T) Metal Distribution M8 CTM content ? Temp-dependent tile-based power density maps ? Per layer metal density map ? Block Power File (separate input) (Dynamic+Leakage) @T3 M5 (Dynamic+Leakage) @T2 M1 ? OD and power info (Dynamic+Leakage) @T1 4 ? 2017 ANSYS, Inc. August 3, 2017 ANSYS UGM 2017 Configuration File(GSR) Setting for Thermal Analysis ? Specify Package Design and Result Directory CPA_FILES { PACKAGE MODEL } ./design.mcm ./adsCTA ? Must-have Option THERMAL_ANALYSIS 1 5 ? 2017 ANSYS, Inc. August 3, 2017 ANSYS UGM 2017 Test Design Example: POP Design 50 C Thermal Board ? DRAM + Die + Interposer/Package + Thermal Board ? Prescribed temperature of 50C on DRAM ? CTM power maps on Die (from RH ) 6 ? 2017 ANSYS, Inc. August 3, 2017 ANSYS UGM 2017 Invoke RedHawk/Totem-CTA Geometry UI Setup Color maps Chip Layout PKG layout view 7 ? 2017 ANSYS, Inc. August 3, 2017 ANSYS UGM 2017 Key Functions for Thermal Analysis 2D LayoutView Run CTA Color Maps Layout Manager ThermalSetup TCL Window ? RedHawk TCL window to input TCL commands ? Layout Manager for layout editing ? Thermal Setup dialog for all CTA setup ? Color Contours to Displ