可编程硬件描述语言VHDL Quartus moore状态机源代码.docx

VHDL Quartus Moore状态机源代码 --Moore状态机输出只依赖于器件的当前状态，与输入信号无关 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; --------------------------------------------- ENTITY MOORE IS PORT ( RST: IN STD_LOGIC;--复位功能 CLK: IN STD_LOGIC;--时钟输入 X: IN STD_LOGIC;--输入 OP: OUT STD_LOGIC--输出 ); END ENTITY MOORE; ---------------------------------------------- ARCHITECTURE A OF MOORE IS TYPE STATE IS (S0,S1,S2,S3); SIGNAL ST: STATE; BEGIN STATE_COMP: PROCESS(RST,CLK) BEGIN IF RST=1 THEN ST = S0; ELSIF rising_edge(clk) THEN CASE ST IS WHEN S0 =OP = 1;--在外部，只与当前状态有关--moore IF X = 0 THEN ST = S0; ELSE ST = S1; END IF; WHEN S1 = IF X = 0 THEN ST = S3; ELSE ST = S2; END IF; OP = 1; WHEN S2= IF X = 0 THEN ST = S2; ELSE ST = S3; END IF; OP = 1; WHEN S3= IF X = 0 THEN ST = S3; ELSE ST = S0; END IF; OP = 0; END CASE; END IF; END PROCESS STATE_COMP; END ARCHITECTURE A;