4-4矩阵键盘(未消抖)verilog.docVIP

4-4矩阵键盘(未消抖)verilog 4-4矩阵键盘(未消抖)verilog PAGE 4-4矩阵键盘(未消抖)verilog 4*4矩阵键盘（未消抖）： module?Matrix_keyboard(clk,in_s,out_s,num); //定义模块端口信息 input??????????clk; input???[3:0]??in_s; output??[3:0]??out_s; output??[4:0]??num; //定义输出信号类型及局部变量 reg?????[4:0]??num; reg?????[1:0]??cnt?=?0; reg?????[1:0]??tmp?=?0; reg?????[3:0]??o_ut_st?=?0; wire????[7:0]??dsample; //将扫描输出和输入信号级联，得到矩阵扫描结果 assign??dsample?=?{o_ut_st,?in_s}; assign??out_s???=?o_ut_st; //产生按钮矩阵的列扫描信号 always??@(posedge?clk) ???begin ???????cnt?=?cnt?+?1b1; ???????case?(cnt) ??????????2b00:?????o_ut_st?=?4b1000; ??????????2b01:?????o_ut_st?=?4b0100; ??????????2b10:?????o_ut_st?=?4b0010; ??????????2b11:?????o_ut_st?=?4b0001;????????? ???????endcase ???end //根据按钮的列扫描信号和行输入信号判断按钮是否被按下 always??@(posedge?clk) ???begin ??????//如果无按钮按下，定义num=16为无效状态 ??????if?(in_s?==?4b0000) ????????begin ???????????if?(tmp?==?3) ?????????????begin ????????????????num?=?16;??//无按键输入，输出16 ????????????????tmp?=?0; ?????????????end ???????????else ?????????????begin ????????????????num?=?num; ????????????????tmp?=?tmp?+?1b1;??//扫描周期,3个时钟周期 ?????????????end ????????end ??????else ????????begin ???????????tmp?=?0; ???????????case?(dsample) ?????????????//第1列扫描结果 ?????????????8b1000_0001:?num?=?0; ?????????????8b1000_0010:?num?=?1; ?????????????8b1000_0100:?num?=?2; ?????????????8b1000_1000:?num?=?3;? ?????????????//第2列扫描结果 ?????????????8b0100_0001:?num?=?4; ?????????????8b0100_0010:?num?=?5; ?????????????8b0100_0100:?num?=?6; ?????????????8b0100_1000:?num?=?7;?? ?????????????//第3列扫描结果 ?????????????8b0010_0001:?num?=?8; ?????????????8b0010_0010:?num?=?9; ?????????????8b0010_0100:?num?=?10; ?????????????8b0010_1000:?num?=?11;?? ?????????????//第4列扫描结果 ?????????????8b0001_0001:?num?=?12; ?????????????8b0001_0010:?num?=?13; ?????????????8b0001_0100:?num?=?14; ?????????????8b0001_1000:?num?=?15;?? ???????????endcase ????????end ???end endmodule??? 独立按键消抖程序： module?Btn_without_shake