EDA中用VHDL语言编程的实验.docxVIP

EDA课程中VHD啲分频程序 ⑴将32KHZ分成1KHz占空比百分之五十 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY fenpin IS PORT (CLK: IN STD_LOGIC; q: OUT STD_LOGIC); END fenpin; ARCHITECTURE arc OF fenpin IS signal wire:std_logic; BEGIN PROCESS (clk) VARIABLEt: INTEGER RANGE 0 TO 31; BEGIN IF clkEVENT AND clk=1 THEN IFt16 THEN cnt:=cnt+1; -- ift=7 then wire=0;end if; 可以通过这绿色字 体修改占空比。 ELSE cnt:=0; -- q=1; wire=not wire; END IF; END IF; END PROCESS; q=wire; END arc; ( 2) 9 进制计数器 程序如下 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT9 IS PORT (CLK1,RST,EN : IN STD_LOGIC; CQ : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); END CNT9; ARCHITECTURE behave OF CNT9 IS BEGIN PROCESS (CLK1,RST,EN) VARIABLE CQI : STD_LOGIC_VECTOR (3 DOWNTO 0); BEGIN IF RST = 1 THEN CQI := (OTHERS =0); ELSIF CLK1EVENT AND CLK1=1 THEN IF EN =1 THEN IF CQI 8 THEN CQI := CQI +1; ELSE CQI := (OTHERS =0); END IF; END IF; END IF; CQ = CQI; END PROCESS; END behave; (3)译码器的程序编写。 USE IEEE.STD_LOGIC_1164.ALL; ENTITY DECL7S IS PORT (D:IN STD_LOGIC_VECTOR(3 DOWNTO 0); A:IN STD_LOGIC_VECTOR(2 DOWNTO 0); B:OUT STD_LOGIC_VECTOR(2 DOWNTO 0); LED7S :OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END DECL7S; ARCHITECTURE one OF DECL7S IS BEGIN B = A; PROCESS(D) BEGIN CASE D IS WHEN 0000 = LED7S = 0111111; WHEN 0001 = LED7S = 0000110; WHEN 0010 = LED7S = 1011011; WHEN 0011 = LED7S = 1001111; WHEN 0100 = LED7S = 1100110; WHEN 0101 = LED7S = 1101101; WHEN 0110 = LED7S = 1111101; WHEN 0111 = LED7S = 0000111; WHEN 1000 = LED7S = 1111111; WHEN 1001 = LED7S = 1101111; WHEN OTHERS = NULL; END CASE; END PROCESS; END; 将上述三个程序主合成一个通过将 32KHZ分成1KHz,在译码器上显示数字0到9. 的主合程序，，，需进行元件例化。。 例化程序如下： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY KON IS PORT(ain,bin,cin:IN STD_LOGIC; AN:IN STD_LOGIC_VECTOR(2 DOWNTO 0); BN:OUT STD_LOGIC_VECTOR(2 DOWNTO 0); YOUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END KON; ARCHITECTURE one OF KON IS COMPONENT fenpin PORT(CLK:IN STD_LOGIC; Q:OUT STD_LOGIC); END COMPONENT; COMPONENT CNT9 PORT(CLK1,RST,EN:IN STD_LOGIC