arm华清远见课件第1天.pptx

ARM Architectureand Processor Cores (By Farsight)  / Agenda Introduction to ARM ARM Architecture Programmer’s Model Introduction to Instruction Sets ARM Processor Cores Appendix ARM Ltd ARM founded in November 1990 12 employees in Cambridge. UK Spun out of Acorn Computers Best known for its range of RISC processor cores designs ARM now has over 1400 employees Based in various locations worldwide ARM Offices Worldwide ARM’s Activities memory SoC Processors System Level IP: Data Engines Fabric Physical IP Software IP Development Tools Connected Community Business Built on Partnership Agenda Introduction to ARM ARM Architecture Programmer’s Model Introduction to Instruction Sets ARM Processor Cores Appendix On chipRAM Example ARM based System ARMProcessor core AMBA AHB ExternalMemory Interface APB Bridge AMBA APB InterruptController ARMPrimecell Peripherals GPIO DMAPort Clocks and Reset Controller ARM core deeply embedded within a SoC External debug via JTAG port Design has both external and internal memories Of varying width, speed and size Includes an interrupt controller Core only support two interrupts Includes Primecell peripherals Licensed from ARM Elements connected using AMBA (Advanced Microcontroller Bus Architecture) DEBUG nIRQ nFIQ FLASH SDRAM ARM based SoC JTAG port allows debug of deeply embedded cores TAP controller provides access to scan chains around core JTAG run control unit (ICE) Converts debugger commands to JTAG signals EmbeddedICE Logic Provides breakpoints and processor/system access ARM Debug Architecture Embedded Trace Macrocell (ETM) Provides a compressed real-time trace of instruction and data accesses made by ARM Trace Port Analyzer (TPA) Allows capture of trace in a deep external buffer Cached Processor Terminology MPU – Memory Protection Unit Controls memory access permissions Controls cacheable and bufferable attributes for memory regions MMU – Memory Management Unit Has all the features of an MPU Also provides