北京科技大学851自动控制原理电子数电课件chapter.pptx

边沿触发方式的特点是：触发器只在时钟跳转时发生翻转，而在CP=1或CP=0期间，输入端的任何变化都不影响输出。;Edge-triggered D flip-flop logic truth table;Figure 7–13 Edge-triggered flip-flop logic symbols (top: positive edge-triggered; bottom: negative edge-triggered). ;Edge-triggered S-R flip-flop ;Edge-triggered D flip-flop ;Edge-triggered D flip-flop ;Edge-triggered J-K flip-flop;Figure 7–14 Operation of a positive edge-triggered S-R flip-flop. ;For a positive edge-triggered R-S flip-flop with input as shown in Figure 7–16 ,determine the Q output to the clock .Assume that Q starts LOW. ;Figure 7–26 Logic symbol for a J-K flip-flop with active-LOW preset and clear inputs. ;For the edge-triggered J-K flip-flop with the input in Figure 7–28 ,Develop the Q output waveform relative to the clock. Assume that Q is initially LOW .;P256: Example 7-9; For a negative edge-triggered J-K flip-flop with input as shown, determine the Q output to the clock . Assume that Q starts LOW.;Figure 7–29 Logic symbols for the 74AHC74 dual positive edge-triggered D flip-flop. ;Figure 7–30 Logic symbols for the 74HC112 dual negative edge-triggered J-K flip-flop. ;Flip-Flop Operating Characteristics （触发器的运行特性）;补充7-2：触发器逻辑功能的描述方法;状态转换图：;JK触发器;D触发器;T触发器;T触发器;补充7-3：触发器逻辑功能的转换;JK触发器转换成T触发器;T触发器转换成T′触发器;D触发器转换成T′触发器;1. 在应用触发器时，要特别注意触发时间，否则很容易造成整个数字系统工作不正常。;7-4 Flip-Flop Applications（触发器的应用） ;7-4-1 Parallel data storage（并行数据存储）;7-4-2 Frequency division（分频）;7-4-3 Counting（计数）;7-4-4 Others;;+5V;CP进入 D触发器;;1.有稳态和暂稳态两个不同的工作状态。 2.在外界触发脉冲作用下，能从稳态翻转到暂稳态,但是经过一定时间以后，又会自动返回原来的稳定状态。 3.暂稳态维持时间的长短取决电路本身的参数，与触发脉冲的宽度和幅度无关。;积分型单稳态触发器的工作原理;;;uA;Non-retriggerable one-shot （不可再触发的单稳态触发器）;Retriggerable one-shot （可再触发的单稳态触发器）;集成单稳组件介绍及单稳态触发器的应用(选学);9;;74LS123输出脉冲的宽度有三种控制方法:; 3. 通过在 A 端或 B 端加再触发脉冲, 可使输出脉冲的宽度加宽: