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第*页 Examples 第*页 Examples 第*页 Examples 第*页 Incorporating the Nulling Resistor into the Miller Compensated Two-Stage Op Amp Circuit 第*页 Design of the Nulling Resistor (M8) 1). In order to place the zero on top of the second pole (p2), the following relationship must hold 2). The resistor, Rz, is realized by the transistor M8 which is operating in the active region because the DC current through it is zero. Therefore, Rz can be written as 3). The bias circuit is designed so that voltage VA is equal to VB. In the saturation region 第*页 Design of the Nulling Resistor (M8) 4). Equating the two expressions for Rz gives 第*页 Examples 第*页 Examples 第*页 An Alternate Form of Nulling Resistor 1). To cancel p2 Which gives 2). In the previous example 第*页 Programmability of the Two-Stage Op Amp The following relationships depend on the bias current, Ibias, in the following manner and allow for programmability after fabrication. Illustration of the Ibias dependence ? 第*页 Simulation of the Electrical Design 第*页 Current Mirror with Different Physical Performances 第*页 1-to-1.5 Transistor Matching 第*页 Reduction of Parasitics The major objective of good layout is to minimize the parasitics that influence the design. Typical parasitics include Capacitors to AC ground Series resistance Capacitive parasitics is minimized by minimizing area and maximizing the distance between the conductor and AC ground Resistance parasitics are minimized by using wide busses and keeping the bus length short For example At 2mΩ/square, a metal run of 1000um and 2um wide will have 1 Ω of resistance. At 1mA this amounts to a 1mV drop which could easily be greater than the least significant bit of an A/D converter 第*页 Technique for Reducing the Overlap Capacitance Square Donut Transistor Can get more W/L in less area with the above geometry 第*页 Chip Voltage Bias Distribution Scheme 第*页 Macromodel Macromodel A macromodel is a model that captures some or all of the performance of a circuit using different component
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