模拟CMOS集成电路设计课件2-1.CMOS Technology.ppt

* 第*页 N-Well CMOS Technology N-Well CMOS Technology (P-Sub 1P2M) P-Type Substrate One layer of Polysilicon, two layers of metal Planarization step Optimal threshold voltages of both p-channel and n-channel transistors Lightly doped drain (LDD) transistors prevent hot-electron effects Good latchup protection N-Well CMOS Technology Fabrication Major Steps Implant and diffuse the n-well Deposition of silicon nitride N-type field (channel stop) implant P-type field (channel stop) implant Grow a thick field oxide (FOX) Grow a thin oxide and deposit polysilicon Remove poly and form LDD spacers Implantation of NMOS S/D and n-material contacts Remove spacers and implant NMOS LDDs Repeat steps 8 and 9 for PMOS Anneal to activate the implanted ions Deposit a thick oxide layer (BPSG – borophosphosilicate glass) Open contacts, deposit first level metal and etch unwanted metal Deposit another interlayer dielectric (CVD SiO2), open vias, deposit second level metal Etch unwanted metal, deposit a passivation layer and open over bonding pads * 第*页 Approximate Side View of CMOS Fabrication * 第*页 Scanning Electron Microscope of a MOSFET Cross-Section * 第*页 Scanning Electron Microscope Showing Metal Levels and Interconnect * 第*页 Summary for CMOS Technology Fabrication is the mean by which the circuit components, both active and passive, are built as an integrated circuit Basic process steps include Oxide grown Thermal diffusion Ion implantation Deposition Etching Epitaxy These steps are restricted to a physical area by the use of photolithography The use of photolithography to apply a process to a certain area is called a masking step The complexity of a process can be measured in the terms of the number of masking steps or masks required to implement the process 700~1100℃ * * * 四氯化硅 硅烷 College of Electronics Information Engineering Analog Integrated Circuit Design CMOS Technology Instructor：韩志刚 * 第*页 Organization (Second Edition of CMOS Analog IC Design) * 第*页 Outline Introduction B