模拟CMOS集成电路设计课件3.Single-Stage Amplifiers.ppt

Output Resistance 第*页 第*页 第*页 Source Follower with Current Source Load 第*页 第*页 3.4 Common Gate 第*页 第*页 Common Gate (cont.) 第*页 Common Gate (cont.) 第*页 第*页 第*页 第*页 Output Resistance of CG 第*页 ππ?ππ 第*页 3.5 Cascode Stage 第*页 第*页 第*页 第*页 第*页 How to increase gain? 1. Cascode structure; 2. For a given bias current, increase L of mosfet. 第*页 Cascode Stage (cont.) 第*页 第*页 第*页 The shielding property of cascodes diminishes if the cascode device enters the triode region. 第*页 3.5.1 Folded Cascode 第*页 第*页 第*页 Homework Exercises Problem 3.1, 3.15, 3.16, 3.17, 3.18, 3.19, 3.20, 3.21, 3.22 * College of Electronics Information Engineering Analog Integrated Circuit Design Chapter 3Single-Stage Amplifiers Instructor：韩志刚 第*页 Analog Design Non-linear system Tradeoffs 3.2 Common-Source Stage 3.2.1 Common-Source Stage with Resistive Load 第*页 第*页 Common Source (cont.) How to maximize the voltage gain of a common-source stage? 第*页 Common Source (cont.) 第*页 Common Source (cont.) 第*页 第*页 3.2.2 Common Source with Diode-Connected Load 第*页 第*页 CS with Diode-Connected Load (cont.) 第*页 Another method– Large signal analysis Gain is independent of bias current! 第*页 What’s the final value of Vout if I1 drops to zero? I1↓ Vov2↓ For small I1, VGS2≈VTH2 Vout ≈ VDD-VTH2 Output characteristic curve of Fig. 3.9 CS with Diode-Connected Load (cont.) 第*页 This implies substantial voltage swing constraint. 第*页 第*页 CS with Current Source Load 第*页 Assuming ro2 large, 3.2.4 CS with Triode Region Load 第*页 CS with Source Degeneration 第*页 CS with Source Degeneration (cont.) 第*页 CS with Source Degeneration (cont.) 第*页 第*页 第*页 CS Output Resistance 第*页 第*页 第*页 Lemma. 第*页 Example 3.6 CS Gain Example 第*页 3.3 Source Follower 第*页 1. Large signal derivation 第*页 第*页 College of Electronics Information Engineering Analog Integrated Circuit Design *