《移动信息工程导论》第10章MSP430定时器和时钟.ppt

BCSCTL2 BCSCTL2 |= SELM_3 + DIVM_3; // MCLK = VLO/8 MCLK SMCLK BCSCTL3 BCSCTL3 |= LFXT1S_2; // Enable VLO as MCLK/ACLK src In MSP430G2553 Interrupt Flag Register 1 (IFG1) OFIFG oscillator-fault flag is set when an oscillator fault (LFXT1OF) is detected. IFG1 = ~OFIFG; // Clear OSCFault flag Sample code 1 for Clock System #include msp430g2553.h void main(void) { WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer P1DIR = 0x40; // P1.6 Output (Green LED) P1OUT = 0; // LED off BCSCTL3 |= LFXT1S_2; // LFXT1 = VLO IFG1 = ~OFIFG; // Clear OSCFault flag _bis_SR_register(SCG1 + SCG0); // Stop DCO BCSCTL2 |= SELM_3 + DIVM_3; // MCLK = VLO/8 while(1) { P1OUT = 0x40; // P1.6 Green LED on _delay_cycles(100); P1OUT = 0; // Green LED off _delay_cycles(5000); } } Sample code 2 for Clock System #include msp430g2553.h void main(void) { WDTCTL = WDTPW + WDTHOLD;// watchdog timer setup if (CALBC1_1MHZ ==0xFF || CALDCO_1MHZ == 0xFF) { while(1); // If cal constants erased, trap CPU!! } BCSCTL1 = CALBC1_1MHZ; // Set range DCOCTL = CALDCO_1MHZ; // Set DCO step + modulation P1DIR = 0x40; // I/O setup P1OUT = 0; BCSCTL3 |= LFXT1S_2; // clock system setup IFG1 = ~OFIFG; //_bis_SR_register(SCG1 + SCG0); BCSCTL2 |= SELM_0 + DIVM_3; while(1) { P1OUT = 0x40; // LED on _delay_cycles(100); P1OUT = 0; // LED off _delay_cycles(5000); } } * * * * * * * * * * * * * To support the lowest power consumption and performance on-demand, the enhanced basic clock system (BCS+) on the MSP430F2xx (like all other MSP430 clock systems) typically provides two clocks. A low frequency auxiliary clock (ACLK) is typically sourced directly from a common 32 k