存储器分析和总结.docxVIP

16*8 的只读存储器的设计方法 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity rom is port(addr:in std_logic_vector(3 downto 0); en:in std_logic; data:out std_logic_vector(7 downto 0)); end; architecture one of rom is type memory is array(0 to 15)of std_logic_vector(7 downto 0); signal data1:memory:=11111101110111001100001000000100,1000101000110100,1001111101011100); signal addr1:integer range 0 to 15; begin addr1=conv_integer(addr); process(en,addr1,addr,data1) begin if en=1 then data=data1(addr1); else data=(others=Z); end if; end process; end; 32*8 随机存储器的设计方法library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity ram is port(addr:in std_logic_vector(4 downto 0); wr:in std_logic; rd:in std_logic; cs:in std_logic; datain:in std_logic_vector(7 downto 0); dataout:out std_logic_vector(7 downto 0)); end; architecture one of ram is type memory is array(0 to 31)of std_logic_vector(7 downto 0); signal data1:memory; signal addr1:integer range 0 to 31; begin addr1=conv_integer(addr); process(wr,cs,addr1,data1,datain) begin if cs=0and wr=1 then data1(addr1)=datain; end if; end process; process(rd,cs,addr1,data1) begin if cs=0and rd=1 then dataout=data1(addr1); else dataout=(others=Z); end if; end process; end; 分频电路的设计 偶数分频电路的设计方法 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity twofenpin is port(clk:in std_logic; div2:out std_logic; div4:out std_logic; div8:out std_logic); end; architecture one of twofenpin is signal cnt:std_logic_vector(2 downto 0); begin process(clk) begin if clkevent and clk=1 then cnt=cnt+1; end if; end process; div2=cnt(0); div4=cnt(1); div8=cnt(2); end;